公开(公告)号：US07871856B2

公开(公告)日：2011-01-18

申请号：US11200037

申请日：2005-08-10

Applicant: Atsushi Yoshimura

Inventor： Atsushi Yoshimura

IPC: H01L21/44

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247

Abstract: A method of manufacturing a stacked-type semiconductor device, comprises: arranging a plurality of stacked chips obtained by stacking semiconductor chips on a plurality of stages on a support substrate; connecting a semiconductor chip of each stage in each stacked chip and the support substrate by wire while performing heating in units of stacked chips; performing plastic molding of each stacked chip; and separating the stacked chips from each other; an apparatus for manufacturing a stacked-type semiconductor device, comprising divided heater blocks formed under a support substrate on which a plurality of stacked chips obtained by stacking a plurality of semiconductor chips are arranged, the divided heater blocks being formed with respect to the stacked chips, and a heating device to selectively transmit heat to a stacked chip subjected to a wire bonding.

Abstract translation: 一种层叠型半导体器件的制造方法，其特征在于，具有：将多个堆叠的芯片配置在支撑基板上的多个级上堆叠半导体芯片而得到的堆叠芯片; 在堆叠的芯片的单元中进行加热时，通过线将每个堆叠的芯片中的每个级的半导体芯片和支撑基板连接; 执行每个堆叠芯片的塑料模制; 并将堆叠的芯片彼此分离; 一种层叠型半导体器件的制造装置，其特征在于，具有形成在支撑基板上的分割加热器块，在所述支撑基板上配置有通过堆叠多个半导体芯片而获得的多个堆叠的芯片，所述分割的加热器块相对于所述堆叠的芯片形成 以及加热装置，用于选择性地将热传递到经过引线接合的堆叠芯片。

公开(公告)号：US20100224705A1

公开(公告)日：2010-09-09

申请号：US12093178

申请日：2007-03-27

Applicant: Naoya Hashii ,  Keishi Nakano ,  Tsuyoshi Munezane ,  Atsushi Yoshimura ,  Manabu Miyaki

Inventor： Naoya Hashii ,  Keishi Nakano ,  Tsuyoshi Munezane ,  Atsushi Yoshimura ,  Manabu Miyaki

IPC: B05B1/30

CPC classification number: F02M61/1853 ,  F02M51/0682 ,  F02M2200/8084 ,  Y10S239/90

Abstract: This invention serves to suppress the deterioration of oil tightness of a valve after welding without any change in the direction of fuel injection even with deformation of a convex portion after welding of an injection opening plate to a valve seat, as well as without any variation in the direction of fuel injection due to welding variation. In this invention, in a fuel injection valve which has a valve body for opening and closing a valve seat, and receives an operation signal from a control unit to operate the valve body so that fuel is injected from a plurality of injection holes formed in an injection hole plate welded through a welded portion to a downstream side of the valve seat while passing through a gap between the valve body and the valve seat, said injection hole plate is formed at its central portion with a convex portion which is substantially axisymmetric with respect to a valve seat axis and which has a circular-arc shaped cross section, and said welded portion is also substantially axisymmetric with respect to said valve seat axis. In addition, inlet portions of said injection holes are disposed in an injection hole arrangement surface diametrically outside of said convex portion and diametrically inside of a valve seat opening inner wall which is a minimum inside diameter of said valve seat, and said injection hole arrangement surface is coplanar with a surface having said welded portion.

Abstract translation: 本发明用于抑制即使在将注射开口板焊接到阀座上的凸部的变形之后，也不会发生任何变化，可以抑制焊接后的阀的油封性的劣化，同时燃料喷射方向没有任何变化 由于焊接变化导致燃油喷射的方向。 在本发明中，在具有用于打开和关闭阀座的阀体的燃料喷射阀中，并接收来自控制单元的操作信号以操作阀体，使得从形成在阀座中的多个喷射孔喷射燃料 喷射孔板在通过阀体和阀座之间的间隙的同时通过焊接部分焊接到阀座的下游侧，所述喷射孔板在其中心部分处形成有凸部，该凸部基本上相对于轴对称 到阀座轴线并且具有圆弧形横截面，并且所述焊接部分也相对于所述阀座轴线基本上是轴对称的。 此外，所述喷射孔的入口部分设置在所述凸部的径向外侧的喷射孔配置表面中，并且直径位于所述阀座的最小内径的阀座开口内壁的内侧，并且所述喷射孔装置表面 与具有所述焊接部分的表面共面。

公开(公告)号：US20100062566A1

公开(公告)日：2010-03-11

申请号：US12585547

申请日：2009-09-17

Applicant: Atsushi Yoshimura ,  Tadanobu Ookubo

Inventor： Atsushi Yoshimura ,  Tadanobu Ookubo

IPC: H01L21/50

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6839 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2225/0651 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: A first semiconductor element is bonded on a substrate. A complex film formed of integrated dicing film and adhesive film is affixed on a rear surface of a semiconductor wafer which is to be second semiconductor elements, the dicing film having a thickness within a range of not less than 50 μm nor more than 140 μm and a room temperature elastic modulus within a range of not less than 30 MPa nor more than 120 MPa, and the adhesive film having a thickness of 30 μm or more and a room temperature elastic modulus before curing within a range of not less than 500 MPa nor more than 1200 MPa. The semiconductor wafer together with the adhesive film is divided into the second semiconductor elements. The second semiconductor element is picked up from the dicing film to be bonded on the first semiconductor element.

公开(公告)号：US20070218586A1

公开(公告)日：2007-09-20

申请号：US11715961

申请日：2007-03-09

Applicant: Atsushi Yoshimura ,  Tadanobu Okubo ,  Shigetaka Onishi

Inventor： Atsushi Yoshimura ,  Tadanobu Okubo ,  Shigetaka Onishi

IPC: H01L21/00

CPC classification number: H01L21/78 ,  B28D5/022 ,  H01L21/67132 ,  H01L21/6835 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752

Abstract: An adhesive layer of which thickness is over 25 μm and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.

Abstract translation: 厚度超过25μm的粘合剂层和切割带层压在半导体晶片的后表面上。 通过使用切割深度到达粘合剂层的第一刀片将半导体晶片与粘合剂层的一部分一起切割。 通过使用切割深度到达切割带并且宽度比第一刀片窄的第二刀片将粘合剂层与切割带的一部分一起切割。 通过用粘合剂层切割半导体晶片而切割的半导体元件从切割带拾取，并且粘附在另一个半导体元件或电路板上。

公开(公告)号：US20070196952A1

公开(公告)日：2007-08-23

申请号：US11651561

申请日：2007-01-10

Applicant: Atsushi Yoshimura ,  Tadanobu Okubo ,  Yasuo Tane

Inventor： Atsushi Yoshimura ,  Tadanobu Okubo ,  Yasuo Tane

IPC: H01L21/00

CPC classification number: H01L21/6838 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A substrate having an element mounting portion is placed on a suction stage having a suction hole. The suction hole is provided so as to suck a region excluding the element mounting portion of the substrate. Otherwise, the suction hole has a hole size of not less than 0.5 mm nor more than 1.0 mm. A fist semiconduct or substrate is sucked with a suction rubber collet with Shore A hardness of not less than 50 nor more than 70. The first semiconductor element is bonded to the element mounting portion of the substrate. A second semiconductor element having an adhesive layer with a remaining volatile content of 0.5% or less is disposed on the first semiconductor substrate. The adhesive layer is heated to a temperature in a range of not less than 120° C. nor more than 150° C. and bonded.

Abstract translation: 具有元件安装部的基板被放置在具有吸入孔的抽吸台上。 吸引孔设置成吸引除基板的元件安装部以外的区域。 否则，吸孔的孔径不小于0.5mm，不大于1.0mm。 第一半导体或基板被吸入具有不低于50且不大于70的肖氏A硬度的吸力橡胶夹头。第一半导体元件结合到基板的元件安装部分。 具有0.5％以下剩余挥发物含量的粘合剂层的第二半导体元件设置在第一半导体衬底上。 将粘合剂层加热至不低于120℃并且不超过150℃的温度。

公开(公告)号：US20070120248A1

公开(公告)日：2007-05-31

申请号：US11602323

申请日：2006-11-21

Applicant: Atsushi Yoshimura ,  Yoshiaki Sugizaki

Inventor： Atsushi Yoshimura ,  Yoshiaki Sugizaki

IPC: H01L23/04

CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06586 ,  H05K1/0269 ,  H05K3/4015 ,  H05K3/4046 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/097 ,  H05K2201/09918 ,  H05K2203/0126 ,  H05K2203/049 ,  H05K2203/166

Abstract: There is disclosed a semiconductor device comprising at least two substrates, at least one wiring being provided in each of the substrates, the substrates being stacked such that major surfaces on one side of each thereof oppose each other and the wirings being connected between the major surfaces, and a plurality of connecting portions being provided adjacent to each other while connected to each wiring on the major surfaces opposing each other, at least one of the connecting portions provided on the same major surface being formed smaller than the adjacent other connecting portion, the connecting portions being provided at positions opposing each other one to one on the major surface, the connecting portions being connected so that the wirings are connected between the major surfaces, one connecting portion of a pair of the connecting portions connected one to one being formed smaller than the other connecting portion.

Abstract translation: 公开了包括至少两个基板的半导体器件，在每个基板中设置至少一个布线，所述基板被堆叠，使得它们的一侧的主表面彼此相对，并且布线连接在主表面之间 并且多个连接部分彼此相邻设置，同时连接到彼此相对的主表面上的每个布线，设置在相同主表面上的至少一个连接部分形成为小于相邻的另一个连接部分， 连接部分设置在主表面上彼此相对的位置处，连接部分连接成使得布线连接在主表面之间，一对连接的一对连接部分的一个连接部分形成较小 比另一个连接部分。

公开(公告)号：US06686222B2

公开(公告)日：2004-02-03

申请号：US10147070

申请日：2002-05-17

Applicant: Shoko Omizo ,  Atsushi Yoshimura ,  Mikio Matsui ,  Takao Sato

Inventor： Shoko Omizo ,  Atsushi Yoshimura ,  Mikio Matsui ,  Takao Sato

IPC: H01L2150

CPC classification number: H01L23/49811 ,  H01L23/544 ,  H01L25/105 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/107 ,  H05K3/4614 ,  H05K3/4638

Abstract: In a semiconductor device manufacturing method, a semiconductor element is mounted on a substrate including first connection electrodes, first interconnections electrically connected to the first connection electrodes and a first alignment mark with the semiconductor element electrically connected to the first interconnections. Then, the substrate having the semiconductor element mounted thereon and a core substrate including second connection electrodes and second interconnections electrically connected to the second connection electrode and having adhesive layers formed on both surfaces thereof are positioned with respect to and stacked on each other based on recognition of the first alignment mark, thermo-compression bonding is performed at temperatures at which an adhesive agent of the adhesive layers is melted, without being cured, to temporarily fix the substrate having the semiconductor element mounted thereon on the core substrate by tackiness of the adhesive agent.

Abstract translation: 在半导体器件制造方法中，半导体元件安装在包括第一连接电极的基板上，与第一连接电极电连接的第一互连和与第一互连电连接的半导体元件的第一对准标记。 然后，在其上安装有半导体元件的基板和包括第二连接电极的芯基板和与第二连接电极电连接并且在其两个表面上形成的粘合剂层的第二互连基于识别而相对于彼此定位 在第一对准标记的温度下，在粘合剂层的粘合剂被熔化而不固化的温度下进行热压接，通过粘合剂的粘性将其上安装有半导体元件的基板临时固定在芯基板上 代理商

公开(公告)号：US06501007B1

公开(公告)日：2002-12-31

申请号：US09335586

申请日：1999-06-18

Applicant: Motoyuki Ashikari ,  Atsushi Yoshimura ,  Masahiro Yano ,  Takashi Matsumoto ,  Takuji Sasaki ,  Jianzhong Wu ,  Kimiko Yamamoto

Inventor： Motoyuki Ashikari ,  Atsushi Yoshimura ,  Masahiro Yano ,  Takashi Matsumoto ,  Takuji Sasaki ,  Jianzhong Wu ,  Kimiko Yamamoto

IPC: C12N1509

CPC classification number: C12N15/8261 ,  C07K14/415 ,  Y02A40/146

Abstract: A method of dwarfing plants comprises controlling the expression of the genes involved in the dwarfism of the plants is provided. A molecule to be utilized for dwarfing plants is also provided. A single gene that causes the d1 mutation, which results in the dwarf abnormality of rice, was identified and isolated from a vast chromosomal region by the map-based cloning technique. This method enables, for example, creating ornamental plants and agricultural products with new commercial values, and therefore is useful especially in the areas of agriculture and horticulture.

Abstract translation: 矮化植物的方法包括控制涉及植物侏儒症的基因的表达。 还提供了用于矮化植物的分子。 通过基于地图的克隆技术，从广泛的染色体区域鉴定并分离导致导致水稻矮化异常的d1突变的单一基因。 该方法例如可以创造具有新商业价值的观赏植物和农产品，因此尤其在农业和园艺领域尤其有用。

公开(公告)号：US5467803A

公开(公告)日：1995-11-21

申请号：US194506

申请日：1994-02-09

Applicant: Atsushi Yoshimura ,  Hiroshi Shibata ,  Fumio Takahashi ,  Kuniaki Tsurushima

Inventor： Atsushi Yoshimura ,  Hiroshi Shibata ,  Fumio Takahashi ,  Kuniaki Tsurushima

IPC: B21D5/01 ,  B21F1/00 ,  H01L21/48 ,  H01L23/50 ,  H05K13/00

CPC classification number: H05K13/0092 ,  H01L21/4842

Abstract: An outer lead bending apparatus comprises a fixed unit, a movable unit movable toward and away from the fixed unit, a first die detachably mounted on one of the fixed unit and movable unit and holding a semiconductor package devise in place, and a second die detachably mounted on the other unit and, when the movable unit is driven toward the fixed unit, bending, together with the first die, the outer leads of the semiconductor package devise into a given configuration.

Abstract translation: 外引线弯曲装置包括固定单元，可朝向和远离固定单元移动的可移动单元，可拆卸地安装在固定单元和可移动单元中的一个上并将半导体封装设置在适当位置的第一模具和可拆卸地安装的第二模具 安装在另一单元上，并且当可移动单元朝向固定单元被驱动时，与第一模具一起弯曲半导体封装的外引线设计成给定的构造。

公开(公告)号：US08796076B2

公开(公告)日：2014-08-05

申请号：US13600153

申请日：2012-08-30

Applicant: Atsushi Yoshimura ,  Shoko Omizo

Inventor： Atsushi Yoshimura ,  Shoko Omizo

IPC: H01L21/00 ,  H01L21/30

CPC classification number: H01L21/6836 ,  H01L21/67132 ,  H01L21/67144 ,  H01L23/3121 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/75745 ,  H01L2224/758 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/181 ,  Y10T156/1744 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.

Abstract translation: 通过曝光和显影形成在半导体晶片的电路侧上的感光表面保护膜和粘合剂层形成开口后，通过将单独的芯片切割成具有感光表面保护膜和粘合剂层的半导体芯片， 半导体晶片。 在第二半导体芯片被吸入夹头放置在第一半导体芯片上之后，第二半导体芯片通过第一表面保护膜和粘合剂层与第一半导体芯片接合。 吸入夹头的吸入侧与现在粘接的半导体芯片之间的吸附侧具有比第二半导体芯片更低的粘附力。