公开(公告)号：US09006029B2

公开(公告)日：2015-04-14

申请号：US13052144

申请日：2011-03-21

Applicant: Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

Inventor： Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/27312 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/29 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.

Abstract translation: 根据一个实施例，公开了一种用于制造半导体器件的方法，该半导体器件包括具有形成在第一主表面上的电极焊盘和设置在第二主表面上的接合层的半导体芯片，以及具有安装在该衬底上的半导体芯片的衬底。 制造方法可以包括在基板的前表面上将接合成形材料的半导体芯片的第二主表面的外边缘接触的部分。 该方法可以包括通过接合层将半导体芯片的第二主表面接合到衬底。

公开(公告)号：US08381706B2

公开(公告)日：2013-02-26

申请号：US12530752

申请日：2008-04-30

Applicant: Yoshihiro Akiyama ,  Atsushi Yoshimura ,  Isao Emi

Inventor： Yoshihiro Akiyama ,  Atsushi Yoshimura ,  Isao Emi

IPC: F02B25/06

CPC classification number: F02F7/006 ,  F01M13/0416 ,  F02M35/10078 ,  F02M35/10111 ,  F02M35/10222 ,  F02M35/10288 ,  F02M35/112

Abstract: A part of a ceiling wall (14) of a head cover (10) that opposes an intake collection chamber (51) is constituted by a concave ceiling wall (20) that defines a concave surface facing the intake collection chamber (51), and the concave ceiling wall (20) is formed with a recessed groove (21) that further recedes toward an inner side of the head cover.

Abstract translation: 与吸气收集室（51）相对的头罩（10）的顶壁（14）的一部分由限定与吸气收集室（51）相对的凹面的凹面顶壁（20）构成， 凹入的顶壁（20）形成有朝向头盖的内侧进一步向后退的凹槽（21）。

公开(公告)号：US20120318431A1

公开(公告)日：2012-12-20

申请号：US13599340

申请日：2012-08-30

Applicant: Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

Inventor： Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC: H01L21/50

CPC classification number: H01L21/6715 ,  H01L21/67109 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/27901 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/743 ,  H01L2224/83191 ,  H01L2224/94 ,  Y10T156/10 ,  H01L2224/27 ,  H01L2924/00

Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.

Abstract translation: 在一个实施例中，公开了一种用于制造半导体器件的方法。 该方法可以包括在将包含树脂和溶剂的粘合材料附着到与包括晶片的电路图案的第一表面相对的第二表面时，加热粘合材料以蒸发溶剂并降低溶剂的蒸气压 气氛面临着接合材料并加热附着的接合材料以形成接合层。

公开(公告)号：US08240281B2

公开(公告)日：2012-08-14

申请号：US12527811

申请日：2008-04-30

Applicant: Yoshihiro Akiyama ,  Atsushi Yoshimura

Inventor： Yoshihiro Akiyama ,  Atsushi Yoshimura

IPC: F01M9/10 ,  F02B77/00

CPC classification number: F01M11/0408 ,  F01M2011/0416 ,  F01M2011/0491 ,  F02F7/006

Abstract: A height of an upper end of an oil outflow prevention wall 25 with respect to the fastening plane 15 is greater in a lower side of the inclination of the fastening plane 15 than in a higher side of the inclination of the fastening plane 15.

Abstract translation: 相对于紧固平面15的油流出防止壁25的上端的高度在紧固平面15的倾斜度的下侧大于​​紧固平面15的倾斜度的上侧。

公开(公告)号：US20110263076A1

公开(公告)日：2011-10-27

申请号：US13067839

申请日：2011-06-29

Applicant: Atsushi Yoshimura ,  Hideko Mukaida

Inventor： Atsushi Yoshimura ,  Hideko Mukaida

IPC: H01L21/50

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20752

Abstract: A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 μm or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.

Abstract translation: 叠层半导体器件包括接合在电路基底上的第一半导体元件。 第一半导体元件经由第一接合线电连接到电路基座的连接部。 第二半导体元件经由厚度为50μm以上的第二粘合剂层接合在第一半导体元件上。 第二粘合层由玻璃化转变温度为135℃以上的绝缘树脂层形成，玻璃化转变温度以下的温度下的线膨胀系数为100ppm以下。

公开(公告)号：US20110079629A1

公开(公告)日：2011-04-07

申请号：US12926774

申请日：2010-12-08

Applicant: Atsushi Yoshimura

Inventor： Atsushi Yoshimura

IPC: B23K37/04 ,  B23K37/00

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247

Abstract: A method of manufacturing a stacked-type semiconductor device, comprises: arranging a plurality of stacked chips obtained by stacking semiconductor chips on a plurality of stages on a support substrate; connecting a semiconductor chip of each stage in each stacked chip and the support substrate by wire while performing heating in units of stacked chips; performing plastic molding of each stacked chip; and separating the stacked chips from each other.An apparatus for manufacturing a stacked-type semiconductor device, comprising divided heater blocks formed under a support substrate on which a plurality of stacked chips obtained by stacking a plurality of semiconductor chips are arranged, the divided heater blocks being formed with respect to the stacked chips, and a heating device to selectively transmit heat to a stacked chip subjected to a wire bonding.

Abstract translation: 一种层叠型半导体器件的制造方法，其特征在于，具有：将多个堆叠的芯片配置在支撑基板上的多个级上堆叠半导体芯片而得到的堆叠芯片; 在堆叠的芯片的单元中进行加热时，通过线将每个堆叠的芯片中的每个级的半导体芯片和支撑基板连接; 执行每个堆叠芯片的塑料模制; 并将堆叠的芯片彼此分离。 一种叠层型半导体器件的制造装置，其特征在于，具有形成在支撑基板的下方的分割加热块，在所述支撑基板上配置有通过堆叠多个半导体芯片而获得的多个堆叠的芯片，所述分割的加热器块相对于所述堆叠的芯片形成 以及加热装置，用于选择性地将热传递到经过引线接合的堆叠芯片。

公开(公告)号：US20100147273A1

公开(公告)日：2010-06-17

申请号：US12530752

申请日：2008-04-30

Applicant: Yoshihiro Akiyama ,  Atsushi Yoshimura ,  Isao Emi

Inventor： Yoshihiro Akiyama ,  Atsushi Yoshimura ,  Isao Emi

IPC: F02B25/06 ,  F02B77/00

CPC classification number: F02F7/006 ,  F01M13/0416 ,  F02M35/10078 ,  F02M35/10111 ,  F02M35/10222 ,  F02M35/10288 ,  F02M35/112

Abstract: A part of a ceiling wall (14) of a head cover (10) that opposes an intake collection chamber (51) is constituted by a concave ceiling wall (20) that defines a concave surface facing the intake collection chamber (51), and the concave ceiling wall (20) is formed with a recessed groove (21) that further recedes toward an inner side of the head cover.

Abstract translation: 与吸气收集室（51）相对的头罩（10）的顶壁（14）的一部分由限定与吸气收集室（51）相对的凹面的凹面顶壁（20）构成， 凹入的顶壁（20）形成有朝向头盖的内侧进一步向后退的凹槽（21）。

公开(公告)号：US07629695B2

公开(公告)日：2009-12-08

申请号：US11132290

申请日：2005-05-19

Applicant: Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

Inventor： Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/14 ,  H01L23/34 ,  H01L23/29 ,  H01L25/11 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Abstract translation: 堆叠的电子部件包括经由第一粘合剂层粘附在基板上的第一电子部件和通过使用第二粘合层粘附的第二电子部件。 第二粘合剂层具有由相同材料形成且具有不同弹性模量的两层结构。 双层结构的第二粘合剂层具有设置在第一电子部件侧的第一层和设置在第二电子部件侧的第二层。 第一层在粘合剂温度下软化或熔化。 第二层在粘合剂温度下保持层状。 根据堆叠的电子元件，可以防止绝缘故障和短路的发生，并且还可以抑制电子部件之间的剥离故障，制造成本的增加等。

公开(公告)号：US20080197470A1

公开(公告)日：2008-08-21

申请号：US12011253

申请日：2008-01-25

Applicant: Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

Inventor： Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Abstract translation: 堆叠的电子部件包括经由第一粘合剂层粘附在基板上的第一电子部件和通过使用第二粘合层粘附的第二电子部件。 第二粘合剂层具有由相同材料形成且具有不同弹性模量的两层结构。 双层结构的第二粘合剂层具有设置在第一电子部件侧的第一层和设置在第二电子部件侧的第二层。 第一层在粘合剂温度下软化或熔化。 第二层在粘合剂温度下保持层状。 根据堆叠的电子元件，可以防止绝缘故障和短路的发生，并且还可以抑制电子部件之间的剥离故障，制造成本的增加等。

公开(公告)号：US20070023875A1

公开(公告)日：2007-02-01

申请号：US11490116

申请日：2006-07-21

Applicant: Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi ,  Atsushi Yoshimura

Inventor： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi ,  Atsushi Yoshimura

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.

Abstract translation: 半导体封装包括具有元件安装部分和引线部分的引线框架。 第一半导体元件和第二半导体元件依次堆叠在元件安装部的至少一侧的主表面上。 用作第二粘合剂层的绝缘树脂层填充在第一半导体元件和第二半导体元件之间。 连接到第一半导体元件的第一接合线的元件侧端部埋设在绝缘树脂层中。