公开(公告)号：US20230253022A1

公开(公告)日：2023-08-10

申请号：US18302560

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/50 ,  G11C29/02 ,  H01L21/822 ,  G11C29/12

CPC classification number: G11C8/08 ,  G11C29/50 ,  G11C29/025 ,  H01L21/8221 ,  G11C29/12 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

公开(公告)号：US11715762B2

公开(公告)日：2023-08-01

申请号：US17220335

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/265

CPC classification number: H01L29/0673 ,  H01L21/2654 ,  H01L27/0924

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US11710782B2

公开(公告)日：2023-07-25

申请号：US17728296

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7851

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

公开(公告)号：US20230231037A1

公开(公告)日：2023-07-20

申请号：US18123596

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/02274 ,  H01L21/823431 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US20230178601A1

公开(公告)日：2023-06-08

申请号：US17832342

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Hsueh-Ju Chen ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: In an embodiment, a semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and a second dipole dopant. The first dipole dopant along a thickness direction of the first gate dielectric layer has a first concentration peak, and the second dipole dopant along the thickness direction of the first gate dielectric layer has a second concentration peak. The second concentration peak is located between the first concentration peak and an upper surface of the first gate dielectric layer. The second concentration peak is offset from the upper surface of the first gate dielectric layer.

公开(公告)号：US11664441B2

公开(公告)日：2023-05-30

申请号：US17238656

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L29/66553 ,  H01L21/0259 ,  H01L21/31116 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

公开(公告)号：US20230144899A1

公开(公告)日：2023-05-11

申请号：US18149224

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L29/42392 ,  H01L29/6653 ,  H01L21/823412 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US20230139258A1

公开(公告)日：2023-05-04

申请号：US17686793

申请日：2022-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hao Hou ,  Che-Hao Chang ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311

Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.

公开(公告)号：US11637180B2

公开(公告)日：2023-04-25

申请号：US17224555

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US20230115763A1

公开(公告)日：2023-04-13

申请号：US18079171

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/40 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: A method includes depositing a first work function tuning layer over a gate dielectric layer using an atomic layer deposition process. The atomic layer deposition process comprises depositing one or more first nitride monolayers; and depositing one or more carbide monolayers over the one or more first nitride monolayers. The method further includes depositing an adhesion layer of the first work function tuning layer; and depositing a conductive material over the adhesion layer.