公开(公告)号：US5428232A

公开(公告)日：1995-06-27

申请号：US246464

申请日：1994-05-18

Applicant: Mitsuhiro Hika ,  Shinichi Tanaka ,  Keigo Aga ,  Hidemi Takakuwa

Inventor： Mitsuhiro Hika ,  Shinichi Tanaka ,  Keigo Aga ,  Hidemi Takakuwa

IPC: H01L21/338 ,  H01L27/02 ,  H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/808 ,  H01L29/812 ,  H03F1/00

CPC classification number: H01L27/0251 ,  H01L29/1075 ,  H01L29/808 ,  H01L29/8124 ,  Y10S257/91

Abstract: A dual gate field effect transistor including first and second gates comprises a conductive region, wherein a potential difference between a second gate electrode section and the conductive region is larger than that between the second gate electrode section and a channel operation region.

Abstract translation: 包括第一和第二栅极的双栅极场效应晶体管包括导电区域，其中第二栅电极部分和导电区域之间的电位差大于第二栅电极部分和沟道操作区域之间的电位差。

公开(公告)号：US5416343A

公开(公告)日：1995-05-16

申请号：US306854

申请日：1994-09-15

Applicant: Jan W. Slotboom ,  Pierre H. Woerlee ,  Reinout Woltjer

Inventor： Jan W. Slotboom ,  Pierre H. Woerlee ,  Reinout Woltjer

IPC: G11C17/16 ,  H01L23/525 ,  H01L27/10 ,  G11C17/00 ,  H01L27/04

CPC classification number: G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/91

Abstract: A semiconductor device includes a number of programmable elements arranged in a matrix of rows and columns. The elements each have a doped semiconductor region (10) and a conductor region (20) which are mutually separated by an insulating layer (8). The conductor region (20) can be a material suitable for forming a rectifying junction (35) with the material of the semiconductor region (10). Within a row, the conductor regions of the programmable elements present therein are coupled to a common row conductor (21 . . . 23), and within a column the semiconductor regions of the programmable elements situated therein are connected to a common column conductor (11 . . . 14). To program an element, a programming voltage V.sub.PROG can be applied between the column and row conductors associated with the element to be programmed during operation, which voltage is greater than the breakdown voltage of at least a portion of the insulating layer (8) situated between the semiconductor region (10) and the conductor region (20) of the element. The programming voltage is applied with such a polarity that majority charge carriers in the semiconductor region (10) are drawn to an interface (4) between the semiconductor region (10) and the insulating layer (8), forming an accumulation layer (31) there. Between the remaining column and row conductors, on the other hand, the programming voltage is offered with an opposite polarity. Thus the programming of the matrix can take place, if so desired, by means of only a single voltage level V.sub.PROG.

Abstract translation: 半导体器件包括以行和列的矩阵排列的多个可编程元件。 这些元件各自具有由绝缘层（8）相互分离的掺杂半导体区域（10）和导体区域（20）。 导体区域（20）可以是适于与半导体区域（10）的材料形成整流结（35）的材料。 在一行内，其中存在的可编程元件的导体区域耦合到公共行导体（21 ... 23），并且在列内，位于其中的可编程元件的半导体区域连接到公共列导体（11 ... 14）。 为了对元件进行编程，编程电压VPROG可以施加在与要在操作期间被编程的元件相关联的列和行导体之间，该电压大于位于第二绝缘层（8）的至少一部分的击穿电压 半导体区域（10）和元件的导体区域（20）。 施加编程电压，使得半导体区域（10）中的多数电荷载流子被吸引到半导体区域（10）和绝缘层（8）之间的界面（4）上，形成蓄积层（31） 那里。 另一方面，在剩余的列和导体之间，以相反的极性提供编程电压。 因此，如果需要，可以仅通过单个电压电平VPROG来进行矩阵的编程。

公开(公告)号：US5170227A

公开(公告)日：1992-12-08

申请号：US493540

申请日：1990-03-14

Applicant: Masahide Kaneko ,  Kenji Noguchi

Inventor： Masahide Kaneko ,  Kenji Noguchi

IPC: H01L21/82 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/112

CPC classification number: H01L27/112 ,  Y10S257/91

Abstract: A method for producing a mask ROM having an array of memory cells in which pn junctions obtained by introducing P-type impurities by ion implantation onto the surface of an N-type electrically conductive layers obtained in turn by introducing N-type impurities into the polysilicon layers are formed as memory cells in a matrix configuration. The polysilicon layers that are to be rendered into the N-type electrically conductive layers are previously monocrystallized by laser annealing. In this manner, the N-type electrically conductive layers into which P-type impurities are introduced by ion implantation at the time of formation of the pn junction are turned into a monocrystalline layer so that the surface of the N-type electrically conductive layers may be uniformly and easily converted into the P-type by this ion implantation. In short, the junction surface of the pn junction used as the memory cell becomes uniform. In this manner, the memory cell having desirable pn junction properties, that is, suited for practical application, may be produced easily.

Abstract translation: 一种具有存储单元阵列的掩模ROM的制造方法，其中通过离子注入将P型杂质引入到通过将N型杂质引入到多晶硅中的N型导电层的表面上而获得的pn结 层形成为矩阵配置的存储单元。 要被制成N型导电层的多晶硅层预先通过激光退火单晶化。 以这种方式，在形成pn结时，通过离子注入引入P型杂质的N型导电层变成单晶层，使得N型导电层的表面可以 通过这种离子注入均匀且容易地转化为P型。 简而言之，用作存储单元的pn结的结表面变得均匀。 以这种方式，可以容易地制造具有期望的pn结特性，即适用于实际应用的存储单元。

公开(公告)号：US5148256A

公开(公告)日：1992-09-15

申请号：US237429

申请日：1981-02-23

Applicant: Hanan Potash ,  Melvyn E. Genter ,  Bruce B. Roesner

Inventor： Hanan Potash ,  Melvyn E. Genter ,  Bruce B. Roesner

IPC: H01L27/112

CPC classification number: H01L27/112 ,  Y10S257/91

Abstract: In the disclosed computer, a plurality of register means for storing digital operands and control signals are in a semiconductor substrate; an arithmetic means for performing functional opertions on the operands are also in the substrate; an insulating layer covers the register means and the arithmetic means; and an interconnect matrix is on top of this insulating layer. The interconnect matrix includes pluralities of logic gates coupled through the insulating layer to the register means and arithmetic means and selectively interconnects them in response to the control signals.

Abstract translation: 在所公开的计算机中，用于存储数字操作数和控制信号的多个寄存器装置在半导体衬底中; 用于对操作数执行功能操作的算术装置也在基板中; 绝缘层覆盖寄存器装置和算术装置; 并且互连矩阵位于该绝缘层的顶部。 互连矩阵包括通过绝缘层耦合到寄存器装置和算术装置的多个逻辑门，并且响应于控制信号选择性地互连它们。

公开(公告)号：US4399450A

公开(公告)日：1983-08-16

申请号：US219059

申请日：1980-12-22

Applicant: Jan Lohstroh

Inventor： Jan Lohstroh

IPC: G11C17/06 ,  G11C17/16 ,  H01L21/8229 ,  H01L23/52 ,  H01L27/10 ,  H01L27/102 ,  H01L29/04 ,  H01L27/04

CPC classification number: H01L27/1021 ,  G11C17/06 ,  G11C17/16 ,  H01L23/52 ,  H01L29/04 ,  H01L2924/0002 ,  Y10S257/91 ,  Y10S257/926

Abstract: In a diode matrix of a permanent memory (ROM) the word line and bit line system is formed by a system of strip-shaped zones of one conductivity type provided in the silicon body and in the another system is formed by polycrystalline silicon tracks of the opposite conductivity type provided on the surface and forming mono-poly p-n junctions with the strip-shaped zones. High packing density and high speed are obtained.

Abstract translation: 在永久存储器（ROM）的二极管矩阵中，字线和位线系统由设置在硅体中的一种导电类型的带状区域系统形成，而另一系统由多晶硅轨道形成 在表面上提供相反的导电类型，并形成与带状区域的单聚点pn结。 获得高填充密度和高速度。

公开(公告)号：US09385114B2

公开(公告)日：2016-07-05

申请号：US14337297

申请日：2014-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Kawae

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/786 ,  H01L29/861 ,  H02H9/04

CPC classification number: H01L27/0255 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/861 ,  H02H9/044 ,  Y10S257/91

Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function φms of a source electrode in contact with the oxide semiconductor, the work function φmd of a drain electrode in contact with the oxide semiconductor, and electron affinity χ of the oxide semiconductor satisfy φms≦χ

Abstract translation: 提供了使用氧化物半导体的非线性元件，例如二极管，并且整流性能良好。 在包含氢浓度小于或等于5×1019 / cm3的氧化物半导体的薄膜晶体管中，与氧化物半导体接触的源电极的功函数＆amp; ms， 与氧化物半导体接触的漏极，氧化物半导体的电子亲和力χ满足＆lt; ms＆nlE;χ＆phgr; md。 通过电连接薄膜晶体管的栅电极和漏电极，可以实现具有更好的整流特性的非线性元件。

公开(公告)号：US08791456B2

公开(公告)日：2014-07-29

申请号：US13835435

申请日：2013-03-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Kawae

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/12

CPC classification number: H01L27/0255 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/861 ,  H02H9/044 ,  Y10S257/91

Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function φms of a source electrode in contact with the oxide semiconductor, the work function φmd of a drain electrode in contact with the oxide semiconductor, and electron affinity χ of the oxide semiconductor satisfy φms≦χ

Abstract translation: 提供了使用氧化物半导体的非线性元件，例如二极管，并且整流性能良好。 在包含氢浓度小于或等于5×1019 / cm3的氧化物半导体的薄膜晶体管中，与氧化物半导体接触的源电极的功函数＆amp; ms， 与氧化物半导体接触的漏极，氧化物半导体的电子亲和力χ满足＆lt; ms＆nlE;χ＆phgr; md。 通过电连接薄膜晶体管的栅电极和漏电极，可以实现具有更好的整流特性的非线性元件。

公开(公告)号：US08212327B2

公开(公告)日：2012-07-03

申请号：US12853172

申请日：2010-08-09

Applicant: Neal T. Kurfiss ,  James E. Carey ,  Xia Li

Inventor： Neal T. Kurfiss ,  James E. Carey ,  Xia Li

IPC: H01L31/00 ,  H01L47/00 ,  H01L29/06 ,  H01L29/24 ,  H01L29/38 ,  H01L29/30 ,  H01L29/36 ,  H01L29/40 ,  H01L31/111 ,  H01L29/732 ,  H01L27/148 ,  H01L31/062 ,  H01L29/861

CPC classification number: H01L27/14603 ,  H01L27/1464 ,  H01L27/14683 ,  H01L31/101 ,  H01L31/18 ,  Y10S257/91

Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract translation: 本公开提供了用于在设备的单侧上配置和构造单个光电检测器或光电检测器阵列的系统和方法，所述光检测器或阵列具有所有制造电路。 二极管的阳极和阴极触点都放置在一侧，而一层激光处理的半导体放置在相反的一侧，以提高成本效益，光子检测和填充因子。

公开(公告)号：US20120080798A1

公开(公告)日：2012-04-05

申请号：US13323120

申请日：2011-12-12

Applicant: Steven T. Harshfield

Inventor： Steven T. Harshfield

IPC: H01L29/43

CPC classification number: H01L29/45 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1691 ,  Y10S257/91

Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract translation: 描述了环状，线性和点接触结构，其显示出比常规圆形接触插塞大大降低由光刻和沉积变化引起的对工艺偏差的敏感性。 在一个实施例中，使用诸如碳或氮化钛的标准导电材料来形成接触。 在替代实施例中，存储材料本身用于形成接触。 这些接触结构可以通过各种方法制造，包括化学机械平面化和小面刻蚀。

公开(公告)号：US08089077B2

公开(公告)日：2012-01-03

申请号：US12296234

申请日：2007-02-21

Applicant: Kenjiro Hamanaka ,  Takahiro Hashimoto

Inventor： Kenjiro Hamanaka ,  Takahiro Hashimoto

IPC: H01L29/18 ,  H01L33/00 ,  H01L29/207 ,  H01L27/146

CPC classification number: B41J2/451 ,  H01L2224/48463 ,  H01L2224/4847 ,  Y10S257/91 ,  Y10S257/911 ,  Y10S257/918

Abstract: A light-emitting element array with the improvement of the light-emitting efficiency and the improvement of the uneven amount of light is provided.A light-emitting element array comprises a light-emitting portion array consisting of a plurality of light-emitting portions linearly arranged in a main scanning direction, and a micro-lens formed on each of the light-emitting portions, wherein the micro-lens has a shape of the length of a sub-scanning direction different from the length of the main scanning direction, and the length of the sub-scanning direction is longer than the length of the main scanning direction, and is 3.5 times or less of the length of the main scanning direction.

Abstract translation: 提供了具有提高发光效率和改善不均匀光量的发光元件阵列。 发光元件阵列包括由沿主扫描方向直线排列的多个发光部分和形成在每个发光部分上的微透镜组成的发光部阵列，其中，微透镜 具有与主扫描方向的长度不同的副扫描方向的长度的形状，并且副扫描方向的长度长于主扫描方向的长度，并且是主扫描方向的3.5倍以下 主扫描方向的长度。