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    SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
    31.
    发明申请
    SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE 审中-公开
    软件可重构数字相位锁定环路架构

    公开(公告)号：US20170005666A1

    公开(公告)日：2017-01-05

    申请号：US15269245

    申请日：2016-09-19

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Roman Staszewski ,  Robert B. Staszewski ,  Fuqiang Shi

    IPC分类号： H03L7/099 ,  H04B1/04 ,  H03L7/197

    CPC分类号： H03L7/0992 ,  G06F7/605 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30181 ,  G06F17/10 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/50 ,  H04B1/04 ,  H04W56/003

    摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

    摘要翻译： 一种基于软件的锁相环（PLL）的新颖有用的装置和方法。 基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。 结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

    Digital phase locked loop (PLL) system with frequency band jump in lock mode
    32.
    发明授权
    Digital phase locked loop (PLL) system with frequency band jump in lock mode 有权
    数字锁相环（PLL）系统，带锁定模式下的频带跳跃

    公开(公告)号：US09520885B1

    公开(公告)日：2016-12-13

    申请号：US14958330

    申请日：2015-12-03

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Zhihong Luo ,  Yi Liang ,  Qi Chen ,  Benjamin Shui Chor Lau

    IPC分类号： H03L7/06 ,  H03L7/099 ,  H03K5/134 ,  H03K5/00

    CPC分类号： H03L7/0992 ,  H03K5/134 ,  H03K2005/00058 ,  H03L7/08 ,  H03L7/099

    摘要： A phase locked loop (PLL) control system is provided that includes a digital controlled oscillator (DCO). The DCO comprises a delay cell chain comprising a number (B) of delay cells, and a load control cell comprising a number (L) of load cells. A system also includes that module that is configured to dynamically adjust the number (B) of delay cells that are activated and part of the delay cell chain and the number (L) of load cells that are switched on, when the PLL control system is operating in a lock mode, to control an amount of delay in the DCO.

    摘要翻译： 提供了包括数字控制振荡器（DCO）的锁相环（PLL）控制系统。 DCO包括延迟单元链，其包括数目（B）个延迟单元，以及负载控制单元，其包括数量（L）个测力传感器。 系统还包括该模块，其被配置为当PLL控制系统为（PLL））时动态地​​调整被激活的延迟单元（B）和延迟单元链的一部分以及打开的负载单元的数量（L） 在锁定模式下操作，以控制DCO中的延迟量。

    DIGITAL SYNCHRONIZER
    33.
    发明申请
    DIGITAL SYNCHRONIZER 有权

    公开(公告)号：US20160294541A1

    公开(公告)日：2016-10-06

    申请号：US15085776

    申请日：2016-03-30

    申请人： NXP B.V.

    发明人： Remco van de Beek ,  Jos Verlinden ,  Ghiath Al-kadi

    IPC分类号： H04L7/033 ,  H04L29/12 ,  H04B5/00

    CPC分类号： H04L7/033 ,  G06F1/0321 ,  H03L7/0992 ,  H03L7/23 ,  H04B5/0031 ,  H04L61/1552

    摘要： A digital synchronizer is disclosed, comprising: a phase locked loop (100) configured to produce an output signal (clkFc) having the same frequency as an input signal (Frx) by selecting a divider ratio (/P) of a frequency divider (130) with a control signal (Pctrl), the frequency divider (130) configured to divide the frequency of a high frequency signal (clkHF) by the divider ratio (/P) to provide the output signal (clkFc); a carrier generator (300) comprising a look-up table (320), the carrier generator (300) configured to generate an oversampled carrier signal using the look-up-table (320) by using the control signal (Pctrl) to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal (clkFc).

    Method and apparatus for fast frequency acquisition in PLL system
    35.
    发明授权
    Method and apparatus for fast frequency acquisition in PLL system 有权
    PLL系统中快速采集的方法和装置

    公开(公告)号：US09362924B1

    公开(公告)日：2016-06-07

    申请号：US14794770

    申请日：2015-07-08

    申请人： Integrated Device Technology, Inc.

    发明人： Changxi Xu ,  Hui Li

    IPC分类号： H03L7/06 ,  H03L7/085 ,  G04F10/00 ,  H03L7/099

    CPC分类号： H03L7/085 ,  G04F10/005 ,  H03J2200/10 ,  H03J2200/15 ,  H03L7/0992 ,  H03L7/10

    摘要： A Method and Apparatus for Fast Frequency Acquisition in PLL System has been disclosed. In one implementation a time to digital converter is used with cycle slip detection for fast acquisition and lock. In one implementation cycle slip detection is applied to determine if a feedback clock from an oscillator is faster than a reference clock or not in one measurement cycle.

    摘要翻译： 已经公开了用于PLL系统中的快速频率采集的方法和装置。 在一个实现中，使用数字转换器的循环滑移检测用于快速采集和锁定。 在一个实现周期中，应用滑动检测来确定来自振荡器的反馈时钟是否比一个测量周期中的参考时钟快。

    Method and Apparatus for Implementing Clock Holdover
    38.
    发明申请
    Method and Apparatus for Implementing Clock Holdover 有权
    实现时钟保持的方法和装置

    公开(公告)号：US20160072619A1

    公开(公告)日：2016-03-10

    申请号：US14778440

    申请日：2013-03-21

    申请人： Telefonaktiebolaget LM Ericsson

    发明人： Kai Zhu

    IPC分类号： H04L7/033 ,  H03L7/08 ,  H03B5/32

    CPC分类号： H04L7/033 ,  H03B5/32 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/087 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/14 ,  H04J3/0688

    摘要： The embodiments disclose a method and apparatus for implementing the clock holdover in the communication system. The apparatus receives an external source clock and outputs an output clock, and comprises a first phase-locked circuit and a second phase-locked circuit. The first phase-locked circuit is configured for taking the external source clock and a first output clock as input and outputting an intermediate clock, the first output clock is outputted by the second phase-locked circuit and fed back to the first phase-locked circuit. The first phase-locked circuit includes a first digital oscillator, and the first digital oscillator is configured to take the first output clock as a working clock to generate the intermediate clock. The second phase-locked circuit is configured for taking the intermediate clock and a local clock fed by a local oscillator as input, and outputting a second output clock.

    摘要翻译： 实施例公开了一种在通信系统中实现时钟保持的方法和装置。 该装置接收一个外部源时钟并输出一个输出时钟，并包括一个第一锁相电路和一个第二锁相电路。 第一锁相电路被配置为将外部源时钟和第一输出时钟作为输入并输出中间时钟，第一输出时钟由第二锁相电路输出并反馈到第一锁相电路 。 第一锁相电路包括第一数字振荡器，第一数字振荡器被配置为将第一输出时钟作为工作时钟产生中间时钟。 第二锁相电路被配置为将中间时钟和由本地振荡器馈送的本地时钟作为输入，并输出第二输出时钟。

    Apparatus and system for digitally controlled oscillator
    39.
    发明授权
    Apparatus and system for digitally controlled oscillator 有权
    数字控制振荡器的装置和系统

    公开(公告)号：US09257994B2

    公开(公告)日：2016-02-09

    申请号：US13995895

    申请日：2012-03-22

    申请人： Amr M. Lotfy ,  Mohamed A. Abdelsalam ,  Mohammed W. El Mahalawy ,  Nasser A. Kurd ,  Mohamed A. Abdelmoneum

    发明人： Amr M. Lotfy ,  Mohamed A. Abdelsalam ,  Mohammed W. El Mahalawy ,  Nasser A. Kurd ,  Mohamed A. Abdelmoneum

    IPC分类号： H03L7/00 ,  H03K3/03 ,  H03L7/081 ,  H03L7/087

    CPC分类号： H03L7/00 ,  H03K3/0315 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0992

    摘要： Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.

    摘要翻译： 这里描述了用于数字控制振荡器（DCO）的装置和系统。 该装置包括电压调节器以提供可调电源; 以及DCO，用于产生输出时钟信号，所述DCO包括一个或多个延迟元件，每个延迟元件可操作以经由所述可调节电源改变其传播延迟，其中每个延迟元件包括具有可调驱动强度的逆变器，其中所述逆变器 由可调电源供电。 该装置还包括数字控制器，用于产生用于指示电压调节器调节可调电源的电压电平的第一信号。

    Phase locked loop circuitry having switched resistor loop filter circuitry, and methods of operating same
    40.
    发明授权
    Phase locked loop circuitry having switched resistor loop filter circuitry, and methods of operating same 有权
    具有开关电阻环路滤波器电路的锁相环电路及其操作方法

    公开(公告)号：US09203417B1

    公开(公告)日：2015-12-01

    申请号：US14466988

    申请日：2014-08-23

    申请人： SiTime Corporation

    发明人： Michael H. Perrott

    IPC分类号： H03L7/06 ,  H03L7/099 ,  H03L7/08 ,  H03L7/085

    CPC分类号： H03L7/0992 ,  H03H19/008 ,  H03L7/0802 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/113 ,  H03L7/183 ,  H03L7/1976

    摘要： Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

    摘要翻译： 用于产生输出信号的锁相环电路，包括振荡器电路，开关电阻器环路滤波器的锁相环电路，其耦合到振荡器电路的输入端（其在一个实施例中包括压控振荡器），包括 包括至少一个电阻器和至少一个电容器的开关电阻器网络，其中所述开关电阻器网络的有效电阻作为控制信号的一个或多个脉冲特性的函数（其中脉冲宽度和频率（或 周期）是控制信号的脉冲特性），具有耦合到开关电阻器环路滤波器的输出的相位检测器电路，以产生控制信号（其可以是周期性的或非周期性的）。 锁相环电路还可以包括提供锁相环电路的锁定状态的频率检测电路。