Removing deterministic phase errors from fractional-N PLLS
    7.
    发明授权
    Removing deterministic phase errors from fractional-N PLLS 有权
    从分数N PLLS中消除确定性相位误差

    公开(公告)号:US09231605B2

    公开(公告)日:2016-01-05

    申请号:US14498438

    申请日:2014-09-26

    Abstract: Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio.

    Abstract translation: 用于相位调整的方法和装置包括相位检测器,其被配置为比较参考时钟和反馈时钟并产生两个输出信号。 两个输出信号的脉冲宽度之间的时间差对应于参考时钟和反馈时钟之间的相位差。 可编程延迟线被配置为根据预测的确定性相位误差来延迟较早的输出信号。 振荡器被配置为根据延迟的输出信号产生反馈信号。 分频器被配置为将振荡器输出的频率除以整数N.整数N被改变以实现平均分数除法比,并且预测的确定性相位误差基于平均分频比和瞬时分频比。

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