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    Transmitter with fully re-assignable segments for reconfigurable FFE taps
    1.
    发明授权
    Transmitter with fully re-assignable segments for reconfigurable FFE taps 有权

    公开(公告)号：US10924310B2

    公开(公告)日：2021-02-16

    申请号：US16277392

    申请日：2019-02-15

    Applicant: International Business Machines Corporation

    Inventor： Zeynep Toprak-Deniz ,  John F. Bulzacchelli ,  Herschel A. Ainspan ,  Jonathan E. Proesel ,  Mounir Meghelli

    IPC: H04L27/01

    Abstract: Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

    DUAL-USE ELECTRO-OPTIC AND THERMO-OPTIC MODULATOR
    6.
    发明申请
    DUAL-USE ELECTRO-OPTIC AND THERMO-OPTIC MODULATOR 审中-公开
    双用电光热调制器

    公开(公告)号：US20160266414A1

    公开(公告)日：2016-09-15

    申请号：US14645568

    申请日：2015-03-12

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Douglas M. Gill ,  Jonathan E. Proesel ,  Jessie C. Rosenberg

    IPC: G02F1/01 ,  G02F1/025

    CPC classification number: G02F1/011 ,  G02F1/0147 ,  G02F1/025

    Abstract: A dual-use thermal and electro-optic modulator. A thermal adjustment hardware set and an electric-field adjustment hardware set adjust the thermal and electrostatic properties of a common waveguide area. The hardware sets are electrically coupled. Signals for each type of modulation are conducted to the waveguide through a shared portion of a communication medium.

    Abstract translation: 一种双用热电光调制器。 热调节硬件组和电场调整硬件组调整公共波导区域的热静电特性。 硬件组件电耦合。 通过通信介质的共享部分向波导传送每种调制类型的信号。

    Transimpedance amplifier
    7.
    发明授权
    Transimpedance amplifier 有权
    互阻放大器

    公开(公告)号：US08994457B2

    公开(公告)日：2015-03-31

    申请号：US14057010

    申请日：2013-10-18

    Applicant: International Business Machines Corporation

    Inventor： Jonathan E. Proesel ,  Alexander V. Rylyakov ,  Clint L. Schow ,  Jose A. Tierno

    IPC: H03F3/08 ,  H03F1/34

    CPC classification number: H03F1/34 ,  H03F3/08 ,  Y10T29/49016

    Abstract: A method of forming a circuit includes forming a transimpedance amplifier having a first input node and a second input node. The method also includes forming a feedback circuit having a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.

    Abstract translation: 形成电路的方法包括形成具有第一输入节点和第二输入节点的跨阻放大器。 该方法还包括形成具有第一晶体管的反馈电路，第一晶体管具有连接到第一输入节点的漏极端子，源极端子和栅极端子，具有连接到第二输入节点的漏极端子的第二晶体管，源极端子， 以及第三晶体管，其漏极端子连接到第一晶体管的源极端子和第二端子的源极端子。

    TRANSMITTER WITH UNIFORM DRIVER SEGMENT ACTIVITY
    8.
    发明公开
    TRANSMITTER WITH UNIFORM DRIVER SEGMENT ACTIVITY 审中-公开

    公开(公告)号：US20230412434A1

    公开(公告)日：2023-12-21

    申请号：US17827425

    申请日：2022-05-27

    Applicant: International Business Machines Corporation

    Inventor： Timothy O. Dickson ,  Martin Cochet ,  Zeynep Toprak-Deniz ,  John Francis Bulzacchelli ,  Jonathan E. Proesel

    IPC: H04L27/04 ,  H03M7/16

    CPC classification number: H04L27/04 ,  H03M7/165

    Abstract: A circuit includes at least three equally weighted drivers; a state variable generator; and an element selector. The latter is coupled to the drivers, has a first input from the generator, has a second input including a plurality of input thermometer-encoded data streams, and has an output of an equal number of thermometer-encoded output data streams supplied to the drivers. The element selector maps the second input to the output dynamically based on a value of the first input from the state variable generator, with an update rate that is no more than one half of a symbol-rate. A serializer is configured to provide serialized data at the symbol rate, with output coupled to one of the second input of the element selector and input of the drivers. The drivers have outputs that are combined to produce an output of the circuit at the symbol rate.

    INTEGER MATRIX MULTIPLICATION BASED ON MIXED SIGNAL CIRCUITS
    9.
    发明申请
    INTEGER MATRIX MULTIPLICATION BASED ON MIXED SIGNAL CIRCUITS 有权

    公开(公告)号：US20220075596A1

    公开(公告)日：2022-03-10

    申请号：US17012916

    申请日：2020-09-04

    Applicant: International Business Machines Corporation

    Inventor： Ankur Agrawal ,  Martin Cochet ,  Jonathan E. Proesel ,  Sergey Rylov ,  Bodhisatwa Sadhu ,  Hyunkyu Ouh

    IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/68 ,  H03M1/46 ,  H03K19/20

    Abstract: A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.

    Differential line time skew compensation for high data rate receivers
    10.
    发明授权
    Differential line time skew compensation for high data rate receivers 有权

    公开(公告)号：US10681802B1

    公开(公告)日：2020-06-09

    申请号：US16560950

    申请日：2019-09-04

    Applicant: International Business Machines Corporation

    Inventor： Troy J. Beukema ,  Jonathan E. Proesel

    IPC: H03K19/0175 ,  H05K1/02 ,  H04L25/14 ,  H04L25/02

    Abstract: P and N termination networks couple a P line and an N line to corresponding receiver inputs. Each termination network includes an electrostatic discharge protection T-coil having an input port coupled to the corresponding line, a terminal port, and a center tap port. At least one of the termination networks further includes at least one delay T-coil having a terminal port, a center tap port, and an input port coupled to the terminal port of a corresponding one of the electrostatic discharge protection T-coils. In a no delay mode, a multiplexer selectively connects the P and N electrostatic discharge protection T-coil center tap ports to the P and N inputs of the receiver. In a delay mode, the multiplexer selectively connects the delay T-coil center tap port to a corresponding one of the P input of the receiver and the N input of the receiver.

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