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    Embedded transmit/receive switch
    1.
    发明授权
    Embedded transmit/receive switch 有权

    公开(公告)号：US11533023B2

    公开(公告)日：2022-12-20

    申请号：US17239527

    申请日：2021-04-23

    Applicant: International Business Machines Corporation

    Inventor： Wooram Lee ,  Bodhisatwa Sadhu

    IPC: H04B1/44 ,  H03F1/42 ,  H03F1/56 ,  H03F3/24 ,  H04B1/48

    Abstract: A TX/RX switch includes a power amplifier (PA), a Low Noise Amplifier (LNA), and an antenna connection. The PA is connected to a PA matching network that has a PA network impedance and a common PA-LNA impedance connected in one or more series-parallel combinations in different embodiments in a transmitting mode. The LNA is connected to a LNA matching network that has a LNA. network impedance and the same common PA-LNA impedance connected in one or more series-parallel combinations in a receive mode. A mode switch can connect the common PA-LNA impedance in different configurations to enable the transmitting and receiving mode respectively. In some embodiments, the mode switch can short or open circuit the connection of the PA matching circuit or the LNA matching circuit to the antenna. In some embodiments, the mode switch can also turn power on or off to the PA or the LNA when the switch is in a mode where the respective amplifier is not selected. Accordingly, with specific design limitations on the common PA-LNA impedance combined with different mode switch configurations of the TX/RX switch components in either the TX or RX mode, the TX/RX switch operates within a design bandwidth without, transmission lines embedded in the TX/RX switch circuitry and provides optimum power transfer from/to the antenna at the antenna connection with reduced noise.

    Compact delay lines and associated circuitry useful for wideband phased-array system
    2.
    发明授权
    Compact delay lines and associated circuitry useful for wideband phased-array system 有权

    公开(公告)号：US11290093B1

    公开(公告)日：2022-03-29

    申请号：US17229181

    申请日：2021-04-13

    Applicant: International Business Machines Corporation

    Inventor： Sudipto Chakraborty ,  Bodhisatwa Sadhu ,  Wooram Lee

    IPC: H03K5/13 ,  H03K5/01 ,  H01Q3/34 ,  H03K5/00

    Abstract: A phased array system includes tunable delay elements having active delay element(s) and passive delay element(s). A second resolution by the passive delay element is smaller than a first resolution by the active delay element, and the resolution corresponds to delay applied to an input signal and has discrete steps for phase over which the delay element can be operated. For multiple sets of tunable delay elements, a calibration process sets, for one set of the delay elements, all but an n-th active delay element and the passive delay element to a first phase, and the n-th active delay element to a second phase. In a second set of the delay elements, all of the active delay elements are set to the first phase and the passive delay element is set to the second phase. A phase difference is detected and adjusted to meet a criterion between the two sets.

    Bipolar transistor frequency doublers at millimeter-wave frequencies
    7.
    发明授权
    Bipolar transistor frequency doublers at millimeter-wave frequencies 有权
    双极晶体管频率以毫米波频率倍增

    公开(公告)号：US09419595B2

    公开(公告)日：2016-08-16

    申请号：US14588532

    申请日：2015-01-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Wooram Lee ,  Alberto Valdes Garcia

    IPC: H03B19/00 ,  H03K5/00 ,  H03B19/14

    CPC classification number: H03K5/00006 ,  H03B19/14

    Abstract: Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency.

    Abstract translation: 频率乘法器包括一对晶体管，每个晶体管通过由传输线形成的相应集电极阻抗连接到公共阻抗。 每个传输线具有在输入信号频率的波长的约四分之一和约八分之一之间的长度，并被调谐以在输入信号频率处在相应晶体管的集电极处产生大的阻抗。 集电极阻抗与公共阻抗之间的输出频率是输入频率的偶数整数倍。

    CIRCULATOR-BASED TUNABLE DELAY LINE
    8.
    发明申请
    CIRCULATOR-BASED TUNABLE DELAY LINE 有权

    公开(公告)号：US20210384597A1

    公开(公告)日：2021-12-09

    申请号：US16896919

    申请日：2020-06-09

    Applicant: International Business Machines Corporation

    Inventor： Wooram Lee ,  Alberto Valdes Garcia

    IPC: H01P1/38 ,  H01P1/18 ,  H01Q3/36

    Abstract: Systems and methods for delaying an input signal are described. A device can receive an input signal. The device can activate a state of at least one circuit element among a plurality of circuit elements. The plurality of circuit elements can be connected to a plurality of segments of a transmission line. The device can output the input signal to the transmission line. The device can receive a reflection of the input signal. A delay between the reflection and input signal can be based on the activated state of the at least one circuit element among the plurality of circuit elements. The device can output the reflection of the input signal as an output signal.

    HARMONIC MULTIPLIER ARCHITECTURE
    10.
    发明申请
    HARMONIC MULTIPLIER ARCHITECTURE 审中-公开

    公开(公告)号：US20190158075A1

    公开(公告)日：2019-05-23

    申请号：US15821743

    申请日：2017-11-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Wooram Lee ,  Bodhisatwa Sadhu ,  Alberto Valdes Garcia

    IPC: H03K5/00 ,  H03K5/15 ,  H03K7/08

    Abstract: A method and system of providing harmonic frequency multiplication are provided. An input signal having a frequency f, is received by a programmable timing circuit. A signal that is in phase with the input signal, is provided at the first output of the programmable timing circuit. A time delayed version of the input signal, having the frequency f, is provided at the second output of the programmable timing circuit. A signal having the frequency f, is provided at the output of a first buffer. A duty cycled controlled signal having the frequency f, is provided at the output of the second buffer. A frequency nf, where n is a positive integer, is provided at the output of the multiplier. A higher-order frequency multiplied signal based on the frequencies f and nf, is provided at the output of a mixer.

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