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    Variable resistance memory device and a method of manufacturing the same
    31.
    发明授权
    Variable resistance memory device and a method of manufacturing the same 有权

    公开(公告)号：US09768232B2

    公开(公告)日：2017-09-19

    申请号：US15297687

    申请日：2016-10-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Ho Eun

    IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

    CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

    Abstract: A variable resistance memory device including a substrate, a first insulation layer disposed on the substrate, first and second conductive lines, and memory units. The first conductive lines are arranged in a first direction on the first insulation layer and extend in a second direction. The second conductive lines are disposed over the first conductive lines, are arranged in the second direction, and extend in the first direction. The memory units are disposed in each area between the first and second conductive lines in a third direction and include a first electrode, a variable resistance pattern, a selection pattern, and a second electrode. The first electrode and the variable resistance pattern include a cross-section having an “L” shape. The variable resistance pattern contacts an upper surface of the first electrode. The second electrode is disposed on the variable resistance pattern. The selection pattern is disposed on the second electrode.

    METHOD OF MANUFACTURING A PCRAM MEMORY
    36.
    发明申请
    METHOD OF MANUFACTURING A PCRAM MEMORY 有权

    公开(公告)号：US20170141307A1

    公开(公告)日：2017-05-18

    申请号：US15348426

    申请日：2016-11-10

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    Inventor： Gabriele NAVARRO

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

    Abstract: A method for manufacturing a PCRAM memory includes forming in a first dielectric layer arranged on a substrate, which includes bottom electrodes, a first rectilinear trench opening onto the set of electrodes; depositing a first active layer in the first trench, such that the first active layer is in electrical contact with the electrodes; covering the first active layer with a second dielectric layer; etching, in the second and second dielectric layers and the first active layer, additional rectilinear trenches oriented perpendicularly to the first trench, to obtain a group of memory devices each including a portion of the first active layer in electrical contact with one of the electrodes; filling the additional trenches with a sacrificial dielectric material; performing an anisotropic etching of the sacrificial material to expose a side surface of each portion of the first active layer; and covering the side surface with a second active layer.

    Methods of fabricating storage elements and structures having edgeless features for programmable layer(s)
    38.
    发明授权
    Methods of fabricating storage elements and structures having edgeless features for programmable layer(s) 有权
    制造具有可编程层的无边缘特征的存储元件和结构的方法

    公开(公告)号：US09595671B1

    公开(公告)日：2017-03-14

    申请号：US15214224

    申请日：2016-07-19

    Applicant: Adesto Technologies Corporation

    Inventor： Kuei Chang Tsai ,  Jeffrey Allan Shields ,  Pascal Verrier

    IPC: H01L21/20 ,  H01L45/00

    CPC classification number: H01L45/1683 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

    Abstract: A method can include forming a bottom structure with a top surface and a side surface that form at least one edge; forming an opening with sloped sides through at least one insulating layer to expose at least a portion of the top surface of the bottom structure; forming a programmable layer over the at least one edge, in contact with the sloped sides of the opening and the top surface of the bottom structure; and forming a top layer over the programmable layer and opening; wherein the programmable layer is programmable between at least two different impedance states.

    Abstract translation: 方法可以包括形成具有顶表面和形成至少一个边缘的侧表面的底部结构; 通过至少一个绝缘层形成具有倾斜侧面的开口以暴露底部结构的顶表面的至少一部分; 在所述至少一个边缘上形成与所述开口的倾斜侧面和所述底部结构的顶表面接触的可编程层; 并在可编程层上形成顶层并打开; 其中所述可编程层可在至少两个不同阻抗状态之间编程。

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