公开(公告)号：US20240282671A1

公开(公告)日：2024-08-22

申请号：US18327998

申请日：2023-06-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan Yu Chen ,  Chun-Yen Lin ,  Hsin Yang Hung ,  Ching-Yu Huang ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Ting-Yun Wu ,  Wei-De Ho ,  Szuya Liao

IPC分类号： H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L23/481 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/66545

摘要： A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

公开(公告)号：US12068378B2

公开(公告)日：2024-08-20

申请号：US18360085

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Yu Huang ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L29/4175 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775

摘要： A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

公开(公告)号：US12068321B2

公开(公告)日：2024-08-20

申请号：US18347023

申请日：2023-07-05

申请人： Samsung Electronics Co., Ltd.

发明人： Sungmin Kim ,  Soonmoon Jung

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/18 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/187 ,  H01L21/28088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer.

公开(公告)号：US20240274677A1

公开(公告)日：2024-08-15

申请号：US18370249

申请日：2023-09-19

申请人： Samsung Electronics Co., Ltd.

发明人： Gunho Jo ,  Chulsung Kim ,  Bomi Kim ,  Heesub Kim ,  Eunho Cho

IPC分类号： H01L29/417 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit device includes fin-type active regions protruding from a substrate and extending lengthwise in a first horizontal direction, source/drain regions respectively arranged on the fin-type active regions, a device isolation film covering both sidewalls of each fin-type active region, an insulating structure covering the source/drain regions and the device isolation film, source/drain contacts respectively arranged on and connected to the source/drain regions and apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a contact isolation insulating film arranged between the source/drain contacts in the second horizontal direction and having a lower surface closer to the substrate than a lower surface of each source/drain contact. At least one of the source/drain contacts includes a first portion extending in a vertical direction toward the substrate along a surface of the contact isolation insulating film.

公开(公告)号：US20240266256A1

公开(公告)日：2024-08-08

申请号：US18369527

申请日：2023-09-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sangmoon Lee ,  Jinbum Kim

IPC分类号： H01L23/48 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： The present disclosure provides semiconductor devices including a field effect transistor (FET) and methods of fabricating the same. In some embodiments, a semiconductor device includes a substrate, a lower power line buried in a lower portion of the substrate, a source/drain pattern on the substrate, and a backside contact that penetrates the substrate and electrically couples the lower power line to the source/drain pattern. The backside contact includes an epitaxial pattern coupled to a lower portion of the source/drain pattern, a contact plug coupled to the lower power line, and a metal-semiconductor compound layer between the epitaxial pattern and the contact plug. The epitaxial pattern includes a top surface that protrudes toward the source/drain pattern.

公开(公告)号：US20240258204A1

公开(公告)日：2024-08-01

申请号：US18486853

申请日：2023-10-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yeonggil KIM ,  Hoonseok SEO ,  Minchul AHN ,  Wookyung YOU ,  Woojin LEE ,  Junghwan CHUN

IPC分类号： H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction on the active region; source/drain regions on the active region and adjacent the gate structure; a backside insulating layer on a lower surface of the substrate; a vertical power structure between adjacent source/drain regions, wherein the vertical power structure extends through the substrate and the backside insulating layer and has an exposed lower surface exposed; an interlayer insulating layer on the backside insulating layer; a backside power structure that extends through the interlayer insulating layer and is connected to the vertical power structure; and a first alignment insulating layer between the backside insulating layer and the interlayer insulating layer, wherein the first alignment insulating layer has a first opening exposing the lower surface of the vertical power structure and contacts the backside power structure.

公开(公告)号：US12051727B2

公开(公告)日：2024-07-30

申请号：US17516715

申请日：2021-11-02

申请人： Au Optronics Corporation

发明人： Po-Yung Liao ,  Yi-Da He

IPC分类号： H01L29/40 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/402 ,  H01L27/1222 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/78621 ,  H01L29/78696

摘要： An active device substrate includes a substrate, a first semiconductor layer, a gate insulating layer, a first gate, a first source, a first drain and a shielding electrode. The first semiconductor layer includes a first heavily doped region, a first lightly doped region, a channel region, a second lightly doped region, and a second heavily doped region that are sequentially connected. The first gate is located on the gate insulating layer and overlaps the channel region. The first source is electrically connected to the first heavily doped region. The first drain is electrically connected to the second heavily doped region. The shielding electrode overlaps the second lightly doped region in a normal direction of the substrate.

公开(公告)号：US20240250161A1

公开(公告)日：2024-07-25

申请号：US18099732

申请日：2023-01-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ming-Heng TSAI ,  Chun-Sheng LIANG ,  Ta-Chun LIN

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545

摘要： Embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked over a substrate, a source/drain feature in contact with each of the plurality of the semiconductor layers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a source/drain contact disposed above the source/drain feature, a gate spacer disposed between the gate electrode layer and the source/drain contact, and an isolation structure extending through the gate electrode layer. The isolation structure includes a first portion having three sides covered by the gate electrode layer, the first portion having a top surface at a first elevation, and a second portion extended outwardly from the first portion, the second portion having a top surface at a second elevation that is lower than the first elevation.

公开(公告)号：US12040334B2

公开(公告)日：2024-07-16

申请号：US17370399

申请日：2021-07-08

申请人： Beihai HKC Optoelectronics Technology Co., Ltd. ,  HKC Corporation Limited

发明人： Yuming Xia ,  En-Tsung Cho ,  Haijiang Yuan

IPC分类号： H01L21/288 ,  H01L27/12 ,  H01L29/417

CPC分类号： H01L27/127 ,  H01L21/2885 ,  H01L27/1292 ,  H01L29/41733

摘要： The present disclosure relates to a source-drain electrode and a method for manufacturing the same, an array substrate and a method for manufacturing the same, and a display mechanism. A method for manufacturing a source-drain electrode includes steps of: disposing a conductive layer on an underlay; forming a photoresist layer on a side of the conductive layer away from the underlay; exposing and then developing the photoresist layer to form grooves passing through the photoresist layer on the photoresist layer, so as to form a patterned photoresist layer; and electrochemically depositing a functional material on the patterned photoresist layer and then removing the photoresist layer to obtain the conductive layer on which a patterned layer is formed, so as to obtain the source-drain electrode. The source-drain electrode manufactured by the above method has a higher conductivity.

公开(公告)号：US20240237324A9

公开(公告)日：2024-07-11

申请号：US18197428

申请日：2023-05-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeewoong KIM

IPC分类号： H10B10/00 ,  H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC分类号： H10B10/125 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696

摘要： A semiconductor memory device includes a substrate including first and second surfaces opposite to each other, a first active pattern on the first surface, a first channel pattern on the first active pattern and a first source/drain pattern connected to the first channel pattern, a gate electrode provided on the first channel pattern and extending in a first direction, the gate electrode adjacent to the first source/drain pattern in a second direction intersecting the first direction, a shared contact provided under the first source/drain pattern and the gate electrode and electrically connecting the first source/drain pattern and the gate electrode to each other, and a backside metal layer on the second surface.