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31.发明公开公开(公告)号：US20240266300A1
公开(公告)日：2024-08-08
申请号：US18107257
申请日：2023-02-08
发明人： Marco Bäßler , Michael Niendorf
IPC分类号： H01L23/00 , H01L23/495 , H01L23/498 , H05K1/18
CPC分类号： H01L23/562 , H01L23/4952 , H01L23/49575 , H01L23/49861 , H05K1/18 , H01L23/3121 , H01L23/4006 , H01L2023/4087 , H01L24/48 , H01L25/0655 , H01L25/072 , H01L2224/48137 , H01L2224/48175 , H05K2201/09063 , H05K2201/09409 , H05K2201/1059
摘要： A power semiconductor module includes: an electrically insulative enclosure; a plurality of power semiconductor dies attached to a substrate inside the electrically insulative enclosure; a lead frame or clip frame disposed above the power semiconductor dies inside the electrically insulative enclosure and electrically connected to the power semiconductor dies; a plurality of contact pins attached to the lead frame or clip frame and protruding through a first side of the electrically insulative enclosure to form an electrical connection interface outside the electrically insulative enclosure; and a plurality of vibration dampeners attached to the lead frame or clip frame. The vibration dampeners protrude through the first side of the electrically insulative enclosure and are separate from the electrical connection interface. The vibration dampeners are configured to dampen vibrations at a circuit board designed to be mounted to the module and do not affect electrical operation of the power semiconductor module.
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公开(公告)号：US20240266271A1
公开(公告)日：2024-08-08
申请号：US18379034
申请日：2023-10-11
发明人： Eun Ho CHO
IPC分类号： H01L23/498 , H01L23/00 , H01L25/065 , H05K1/11
CPC分类号： H01L23/49838 , H01L23/49816 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0655 , H05K1/111 , H01L2224/08155 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/1431 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H05K2201/10734
摘要： A semiconductor package includes a package substrate, an interposer on the package substrate and including first upper pads, the first upper pads including a first set of upper pads and a second set of upper pads, a first semiconductor chip on the interposer and comprising first lower pads respectively connected to the first set of upper pads, a plurality of first pins on a first top surface of the first semiconductor chip and substantially uniformly spaced apart by a first distance, and a plurality of second pins on the first top surface of the first semiconductor chip and substantially uniformly spaced apart by a second distance that is different from the first distance, where the first top surface of the first semiconductor chip includes a first region and a second region that does not overlap the first region.
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公开(公告)号：US20240266267A1
公开(公告)日：2024-08-08
申请号：US18637737
申请日：2024-04-17
发明人： PEI CHENG FAN
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/486 , H01L23/49833 , H01L23/49838 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L24/04 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/73 , H01L2224/0401 , H01L2224/05551 , H01L2224/05555 , H01L2224/05563 , H01L2224/13111 , H01L2224/13139 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/73204
摘要： The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.
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公开(公告)号：US12055777B2
公开(公告)日：2024-08-06
申请号：US17723174
申请日：2022-04-18
申请人： Intel Corporation
发明人： Peng Li , Joel Martinez , Jon Long
IPC分类号： G02B6/43 , H01L23/00 , H01L23/498 , H01L23/538 , H01L25/065 , H04B10/40
CPC分类号： G02B6/43 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5385 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0655 , H04B10/40 , H01L24/13 , H01L24/16 , H01L2224/13101 , H01L2224/1403 , H01L2224/16225 , H01L2924/10253 , H01L2924/15311 , H01L2924/3511 , H01L2924/3511 , H01L2924/00 , H01L2224/13101 , H01L2924/014 , H01L2924/00014 , H01L2924/10253 , H01L2924/00012
摘要： A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.
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公开(公告)号：US20240260195A1
公开(公告)日：2024-08-01
申请号：US18419573
申请日：2024-01-23
发明人： HONG-CHI YU , CHUN-JUNG LIN , RUEI-TING GU
CPC分类号： H05K1/181 , H01L25/0655 , H01L25/50 , H01L23/3121 , H01L24/16 , H01L2224/16225 , H05K1/117 , H05K2201/10159 , H05K2201/10545 , H10B80/00
摘要： An embedded dual in-line memory module (DIMM) is provided. The memory module includes a printed circuit board (PCB), a first memory chip set, and a second memory chip set. A plurality of memory chips of the first memory chip set is arranged and electrically connected to a first circuit layer of the PCB by flip chip. A plurality of memory chips of the second memory chip set is arranged and electrically connected to a second circuit layer of the PCB by flip chip. The respective chips are directly disposed on the PCB by flip chip. Thereby the memory module has a condition that there is no metal wire for electrical connection generated by wire bonding. This helps cost reduction at manufacturing end and improves electrical performance.
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公开(公告)号：US20240258183A1
公开(公告)日：2024-08-01
申请号：US18632047
申请日：2024-04-10
申请人： Intel Corporation
发明人： Edvin CETEGEN , Jacob VEHONSKY , Nicholas S. HAEHN , Thomas HEATON , Steve S. CHO , Rahul JAIN , Tarek IBRAHIM , Antariksh Rao Pratap SINGH , Nicholas NEAL , Sergio CHAN ARGUEDAS , Vipul MEHTA
IPC分类号： H01L23/16 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
CPC分类号： H01L23/16 , H01L23/3185 , H01L23/49822 , H01L23/49838 , H01L24/16 , H01L25/0655 , H01L2224/16227 , H01L2924/18161
摘要： Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.
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公开(公告)号：US12051651B2
公开(公告)日：2024-07-30
申请号：US18202136
申请日：2023-05-25
申请人： Intel Corporation
IPC分类号： H01L23/48 , H01L21/48 , H01L23/498 , H01L23/538 , H01L23/64 , H01L25/00 , H01L25/065 , H01L23/00
CPC分类号： H01L23/5383 , H01L21/4857 , H01L23/49822 , H01L23/642 , H01L23/647 , H01L25/065 , H01L25/0655 , H01L25/50 , H01L23/49816 , H01L23/5385 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192
摘要： An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.
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公开(公告)号：US20240250069A1
公开(公告)日：2024-07-25
申请号：US18624686
申请日：2024-04-02
发明人： Shu-Shen YEH , Po-Chen LAI , Che-Chia YANG , Li-Ling LIAO , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L25/065 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/498
CPC分类号： H01L25/0655 , H01L21/4857 , H01L21/563 , H01L21/78 , H01L23/3185 , H01L23/49822
摘要： A package structure is provided. The package structure includes a chip structure having opposite surfaces with different widths. The chip structure has an inclined sidewall between the opposite surfaces. The package structure also includes a protective layer laterally surrounding the chip structure.
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公开(公告)号：US12047041B2
公开(公告)日：2024-07-23
申请号：US17490798
申请日：2021-09-30
发明人： Shunji Yoshimi , Yuji Takematsu , Yukiya Yamaguchi , Takanori Uejima , Satoshi Goto , Satoshi Arayashiki
IPC分类号： H03F3/21 , H01L23/522 , H01L23/538 , H01L25/065 , H01L29/737 , H03F3/195
CPC分类号： H03F3/21 , H01L23/5226 , H01L23/5383 , H01L25/0655 , H01L25/0657 , H01L29/7371 , H01L2225/06517 , H03F2200/294 , H03F2200/451
摘要： A semiconductor devices comprises a first member including a first circuit partially formed by an elemental semiconductor element at a surface layer, a first conductive raised portion at the first member, and a second member smaller than the first member in plan view joined to the first member. The second member includes a second circuit partially formed by a compound semiconductor element. A second conductive raised portion is at the second member. A power amplifier includes a first-stage amplifier circuit included in the first or second circuit and a second-stage amplifier circuit included in the second circuit. The first circuit includes a first switch for inputting to the first-stage amplifier circuit a radio-frequency signal inputted to a selected contact, a control circuit to control the first- and second-stage amplifier circuits, and a second switch for outputting from a selected contact a radio-frequency signal outputted by the second-stage amplifier circuit.
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公开(公告)号：US12046530B2
公开(公告)日：2024-07-23
申请号：US17558508
申请日：2021-12-21
发明人： Je-Hsiung Lan , Jonghae Kim , Ranadeep Dutta
IPC分类号： H01L21/48 , H01L23/367 , H01L25/00 , H01L25/065
CPC分类号： H01L23/3677 , H01L21/4871 , H01L25/0655 , H01L25/50
摘要： Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.
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