公开(公告)号：US20180253353A1

公开(公告)日：2018-09-06

申请号：US15698836

申请日：2017-09-08

Applicant: Toshiba Memory Corporation

Inventor： Yasuhiro TAKASE

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/3738 ,  H03M13/4138 ,  H03M13/45 ,  H03M13/6325

Abstract: According to one embodiment, a memory controller includes: a memory I/F that reads a codeword written in a NAND memory as any one of hard-bit information, first soft-bit information, and second soft-bit information; a codeword processor that generates a codeword of an first soft-decision value from the first soft-bit information, and generates a codeword of a second soft-decision value from the second soft-bit information; a first decoder that executes hard-decision decoding on a codeword of a hard-decision value configured from the hard-bit information; a second decoder that executes first soft-decision decoding on the codeword of the first soft-decision value; and a third decoder that executes second soft-decision decoding on the codeword of the second soft-decision value, wherein the first soft-bit information includes information having a first number of bits greater than the number of bits of the hard-bit information, and the second soft-bit information includes information having a second number of bits greater than the number of bits of the first soft-bit information.

公开(公告)号：US20180247697A1

公开(公告)日：2018-08-30

申请号：US15720525

申请日：2017-09-29

Applicant: SK hynix Inc.

Inventor： Hee Youl LEE

IPC: G11C29/08 ,  G11C29/50 ,  G11C11/413

CPC classification number: G11C29/08 ,  G11C8/08 ,  G11C11/413 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/50 ,  G11C2029/0411 ,  G11C2029/5004

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells coupled between a common source line and a bit line, and a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines, wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on.

公开(公告)号：US10055288B2

公开(公告)日：2018-08-21

申请号：US15225846

申请日：2016-08-02

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiin Lai ,  Jiangli Zhu

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  G11C16/04 ,  G11C29/04

CPC classification number: G06F11/1072 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

公开(公告)号：US20180232274A1

公开(公告)日：2018-08-16

申请号：US15954535

申请日：2018-04-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Daisuke HASHIMOTO ,  Hironori UCHIKAWA

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/11 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/152 ,  H03M13/19 ,  H03M13/2909 ,  H03M13/293

Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.

公开(公告)号：US20180232273A1

公开(公告)日：2018-08-16

申请号：US15951483

申请日：2018-04-12

Applicant: Invensas Corporation

Inventor： William C. Plants

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G11C29/52 ,  G11C2029/0411

Abstract: The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both NVM manufacturers and NVM users. Multiple methods of preferred state encoding (PSE) and/or error correction code (ECC) encoding may be used in different pages or blocks in the same NVM device for different purposes which may be dependent on the nature of the data to be stored.

公开(公告)号：US20180197584A1

公开(公告)日：2018-07-12

申请号：US15913131

申请日：2018-03-06

Applicant: Futurewei Technologies, Inc.

Inventor： Xiaobing Lee ,  Feng Yang ,  Yu Meng ,  Yunxiang Wu

IPC: G11C7/10 ,  G06F11/14 ,  G06F3/06 ,  G11C5/04 ,  G06F12/02 ,  G06F13/16 ,  G11C8/18

CPC classification number: G11C7/10 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0655 ,  G06F3/0685 ,  G06F11/1469 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1673 ,  G06F2212/217 ,  G11C5/04 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/005 ,  G11C2029/0411 ,  G11C2207/2245

Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.

公开(公告)号：US10020822B2

公开(公告)日：2018-07-10

申请号：US15323598

申请日：2015-07-20

Applicant: Rensselaer Polytechnic Institute

Inventor： Tong Zhang ,  Hao Wang

IPC: H03M13/15 ,  G06F3/06 ,  G06F11/10 ,  H03M13/00

CPC classification number: H03M13/154 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1076 ,  G11C11/40 ,  G11C29/028 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1575 ,  H03M13/6502

Abstract: A system and method of providing error tolerant memory access operations on a memory device. A method is disclosed including: providing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets, wherein each tiered set includes addresses having a number of weak memory cells; receiving a target address for a memory read operation; reading data from a virtual repair memory if the target address belongs to a first tiered set of addresses having a number of weak memory cells exceeding a threshold; and if the target address does not belong the first tiered set of addresses, reading data from the memory device and alternatively performing (a) an error correction and error detection (ECED) operation and (b) a target address look up operation, at different settings, until an error free result is obtained.

公开(公告)号：US10019367B2

公开(公告)日：2018-07-10

申请号：US15479795

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Chankyung Kim ,  Jongpil Son

IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0844 ,  G06F12/0884

CPC classification number: G06F12/0846 ,  G06F11/1064 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0844 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/128 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40607 ,  G11C11/4093 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/32 ,  G11C29/26 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5002 ,  G11C2207/2245

Abstract: A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.

公开(公告)号：US20180165993A1

公开(公告)日：2018-06-14

申请号：US15379216

申请日：2016-12-14

Applicant: Western Digital Technologies, Inc.

Inventor： Zvonimir Z. BANDIC ,  Robert Eugeniu MATEESCU ,  Minghai QIN ,  Chao SUN

IPC: G09C5/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G09C1/00 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.

公开(公告)号：US20180152203A1

公开(公告)日：2018-05-31

申请号：US15627758

申请日：2017-06-20

Applicant: SK hynix Inc.

Inventor： Soo Jin KIM

IPC: H03M13/15 ,  H03M13/07 ,  G11C16/34 ,  G11C29/04

CPC classification number: H03M13/151 ,  G11C16/3404 ,  G11C29/04 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/07 ,  H03M13/152 ,  H03M13/153 ,  H03M13/1595 ,  H03M13/6561

Abstract: An error correction circuit includes a syndrome calculator suitable for generating syndromes from an “n”-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.