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公开(公告)号：US20200264953A1
公开(公告)日：2020-08-20
申请号：US16281039
申请日：2019-02-20
Applicant: Western Digital Technologies, Inc.
Inventor： Minghai QIN
Abstract: Systems and methods are disclosed for error correction in data storage devices. In some implementations, a method is provided. The method includes obtaining configuration data indicating a logical arrangement for a set of blocks. The logical arrangement includes rows and columns of blocks. The configuration data also indicates a number of row parity blocks in a set of row parity blocks and a number of diagonal parity blocks in a set of diagonal parity blocks. The method also includes configuring a set of storage devices based on the configuration data, wherein a first number of data blocks in the set of diagonal parity blocks is less than a second number of data blocks in a column.
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公开(公告)号：US20180181317A1
公开(公告)日：2018-06-28
申请号：US15388623
申请日：2016-12-22
Applicant: Western Digital Technologies, Inc.
Inventor： Zvonimir Z. BANDIC , Kiran Kumar GUNNAM , Minghai QIN
CPC classification number: G11C29/52 , G06F11/1072
Abstract: The present disclosure generally relates to methods of reading data from a memory device using non-binary ECCs. The memory device includes multiple memory cells where each memory cell has multiple pages that are arranged in distinct layouts for physical addresses thereof. When a read request is received from a host device to obtain data from a specific page of a specific memory cell of a memory device, rather than reading the data from all pages of the memory cell, the data can be read from just the desired page and then decoded. Following decoding, the data can be delivered to the host device. Because only the data from a specific page of a memory cell is read, rather than the entire memory cell, the read latency is reduced when compared to reading the entire memory cell.
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公开(公告)号：US20180173460A1
公开(公告)日：2018-06-21
申请号：US15380430
申请日：2016-12-15
Applicant: Western Digital Technologies, Inc.
Inventor： Zvonimir Z. BANDIC , Minghai QIN , Chao SUN , Dejan VUCINIC
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/061 , G06F3/0688
Abstract: The present disclosure generally relates to a flash storage system, and more particularly to a scheduler in the flash storage system. The flash storage system includes a device queue, a scheduler coupled to the device queue, and a plurality of dies. In one embodiment, the scheduler pushes commands from the device queue into one or more dies of the plurality of dies for processing in read command phase and write command phase. By separately pushing read commands and write commands into dies for processing, latency is decreased and TOPS is increased.
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公开(公告)号：US20240095540A1
公开(公告)日：2024-03-21
申请号：US18343173
申请日：2023-06-28
Applicant: Western Digital Technologies, Inc.
Inventor： Minghai QIN , Jaco HOFMANN , Chao SUN , Qingbo WANG , Dejan VUCINIC
IPC: G06N3/098
CPC classification number: G06N3/098
Abstract: Methods and apparatus for processing data in a distributed inference scheme based on sparse inputs. An example method includes receiving an input at a first node. A first sparsified input is generated for a second node based on a set of features associated with the second node, which are identified based on a weight mask having non-zero values for weights associated with features upon which processing by the second node depends and zeroed values for weights associated with other features. The first sparsified input is transmitted to the second node for generating an output of the second node. A second sparsified input is received from the second node and combined into a combined input. The combined input is processed into an output of the first node. The neural network is configured to generate an inference based on processing the outputs of the first node and the second node.
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公开(公告)号：US20180351577A1
公开(公告)日：2018-12-06
申请号：US15608174
申请日：2017-05-30
Applicant: Western Digital Technologies, Inc.
Inventor： Minghai QIN , Zvonimir Z. BANDIC , Dejan VUCINIC
Abstract: Embodiments of a data storage device include a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a decoder configured to decode a non-binary code, such as a low-density parity-check (LDPC) code. The decoder decodes the code by generating variable-node-to-check-node message vectors and by generating check-node-to-variable-node message vectors. When generating variable-node-to-check-node message vectors, the decoder considering a first number and then a second greater number of components of the variable-node-to-check-node message vectors. Embodiments of a method of decoding non-binary codes, such as non-binary LDPC codes, include generating variable node message vectors and check node message vectors in logarithm form. The check node message vectors are generated at a first complexity less than a full complexity of considering all components of the variable node message vectors and generated at a second complexity greater than the first complexity.
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公开(公告)号：US20180165032A1
公开(公告)日：2018-06-14
申请号：US15379203
申请日：2016-12-14
Applicant: Western Digital Technologies, Inc.
Inventor： Zvonimir Z. BANDIC , Minghai QIN , Chao SUN
CPC classification number: G06F3/0634 , G06F3/0608 , G06F3/0611 , G06F3/0679 , G06F3/0688 , G11C11/5621 , G11C11/5671 , G11C16/10 , G11C16/26 , G11C2211/5641
Abstract: The present disclosure generally relates to a method for reading and writing data for archival applications in a multiple-level cell memory device. In one embodiment, a method includes operating the multiple-level cell memory device in a single-level cell mode until all blocks are written, changing the single-level cell mode to a first multiple-level cell mode to generate additional space in each block, and operating the multiple-level cell device in the first multiple-level cell mode until all additional space in each block is written. Since the read and write speeds are faster in the single-level cell mode, read and write performances of the multiple-level cell memory device are improved.
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公开(公告)号：US20180373626A1
公开(公告)日：2018-12-27
申请号：US15631034
申请日：2017-06-23
Applicant: Western Digital Technologies, Inc.
Inventor： Chao SUN , Adam MANZANARES , Minghai QIN , Dejan VUCINIC , Frank R. CHU
CPC classification number: G06F12/0246 , G06F3/061 , G06F3/0631 , G06F3/0637 , G06F3/0649 , G06F3/0653 , G06F3/0679 , G06F3/068 , G06F3/0685 , G06F12/0638 , G06F13/1668
Abstract: A device having a controller configured to interface with a host, a storage class memory configured to interface with the controller and a flash memory configured to interface with the controller, wherein both the storage class memory and the flash memory are configured to store data, and wherein the controller is configured to separate the data according to latency critical data and non-latency critical data.
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公开(公告)号：US20180182453A1
公开(公告)日：2018-06-28
申请号：US15472326
申请日：2017-03-29
Applicant: Western Digital Technologies, Inc.
Inventor： Zvonimir Z. BANDIC , Robert Eugeniu MATEESCU , Minghai QIN , Chao SUN
IPC: G11C11/56
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/08 , G11C2211/5641
Abstract: In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.
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9.发明申请
公开(公告)号：US20170141878A1
公开(公告)日：2017-05-18
申请号：US14942516
申请日：2015-11-16
Applicant: Western Digital Technologies, Inc.
Inventor： Dejan VUCINIC , Robert MATEESCU , Minghai QIN , Zvonimir Z. BANDIC
CPC classification number: H04L1/0057 , G06F11/10 , H03M13/152
Abstract: Methods and systems for performing operations in a communications protocol are provided. A memory controller can retrieve data packets from the memory and send each retrieved data packet to a host, as each data packet is retrieved. The memory controller can retrieve an error correcting code (ECC) packet corresponding to the retrieved data packets and execute an ECC algorithm to identify and correct potential errors in the retrieved plurality of data packets. The memory controller can send any corrected data packets to the host if any of the retrieved data packets had errors and send a completion packet to the host.
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公开(公告)号：US20200099401A1
公开(公告)日：2020-03-26
申请号：US16141806
申请日：2018-09-25
Applicant: Western Digital Technologies, Inc.
Inventor： Minghai QIN
Abstract: Systems and methods are disclosed for decoding data. A first block of data may be obtained from a storage medium or received from a computing device. The first block of data includes a first codeword generated based on an error correction code. A first set of likelihood values is obtained from a neural network. The first set of likelihood values indicates probabilities that the first codeword will be decoded into one of a plurality of decoded values. A second set of likelihood values is obtained from a decoder based on the first block of data. The second set of likelihood values indicates probabilities that the first codeword will be decoded into one of the plurality of decoded values. The first codeword is decoded to obtain a decoded value based on the first set of likelihood values and the second set of likelihood values.
