公开(公告)号：US20050101093A1

公开(公告)日：2005-05-12

申请号：US10705500

申请日：2003-11-12

Applicant: Ya-Lun Cheng ,  Chin-Cheng Chien ,  Neng-Hui Yang ,  Yu-Kun Chen

Inventor： Ya-Lun Cheng ,  Chin-Cheng Chien ,  Neng-Hui Yang ,  Yu-Kun Chen

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/311 ,  H01L21/336 ,  H01L21/461 ,  H01L29/78

CPC classification number: H01L21/02052 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A method for preventing to form a spacer undercut in SEG pre-clean process is provided. This present invention utilizes HFEG solution to etch the first spacer and the second spacer simultaneously, which can prevent from producing a spacer undercut, meanwhile; a native oxide layer upon a surface of a semiconductor substrate is removed. Hence, the clean surface on the semiconductor substrate is obtained. This method includes the steps as follows: Firstly, the native oxide layer upon the surface of the semiconductor substrate is removed by DHF (HF in deionized water) solution. Then, etching the first spacer and the second spacer at the same time by HFEG (HF diluted by ethylene glycol) solution. Also, the native oxide upon the semiconductor substrate is removed. Therefore, it obtains the clean semiconductor surface without a serious spacer undercut.

Abstract translation: 提供了一种防止在SEG预清洁工艺中形成间隔件底切的方法。 本发明利用HFEG溶液同时蚀刻第一间隔物和第二间隔物，同时可防止产生间隔物底切; 去除在半导体衬底的表面上的自然氧化物层。 因此，获得半导体衬底上的清洁表面。 该方法包括以下步骤：首先，通过DHF（去离子水中的HF）溶液除去半导体衬底表面上的自然氧化物层。 然后，通过HFEG（用乙二醇稀释的HF）溶液同时蚀刻第一间隔物和第二间隔物。 此外，去除半导体衬底上的自然氧化物。 因此，它获得清洁的半导体表面而没有严重的间隔物底切。

公开(公告)号：US06853417B2

公开(公告)日：2005-02-08

申请号：US10178523

申请日：2002-06-25

Applicant: Chin-Cheng Chien ,  Cheng-Jen Chu

Inventor： Chin-Cheng Chien ,  Cheng-Jen Chu

IPC: G02B5/02 ,  G02B5/08 ,  G02F1/1335 ,  G03F1/00 ,  G03F1/70 ,  G03F7/20

CPC classification number: G02F1/133553

Abstract: A method of fabricating a slant reflector with a bump structure, includes the steps of: providing a substrate; forming a layer of photosensitive material on the substrate; patterning the photosensitive material to form a plurality of trapezoidal bumps that have different bottom areas and that are joined to each other at their bottoms; and smoothing the trapezoidal bumps to form a bump structure with an inclined angle. The invention utilizes a photo-mask with a particular pattern and optical diffraction to fabricate the bump structure in a simple way.

Abstract translation: 制造具有凸块结构的倾斜反射体的方法包括以下步骤：提供基板; 在基板上形成感光材料层; 图案化感光材料以形成具有不同底部区域并且在其底部彼此连接的多个梯形凸块; 并平滑梯形凸块以形成具有倾斜角的凸块结构。 本发明利用具有特定图案和光学衍射的光掩模以简单的方式制造凸块结构。

公开(公告)号：US06819370B2

公开(公告)日：2004-11-16

申请号：US10249671

申请日：2003-04-29

Applicant: Wen-Jyh Sah ,  Chin-Cheng Chien ,  Hsin-Hung Chen

Inventor： Wen-Jyh Sah ,  Chin-Cheng Chien ,  Hsin-Hung Chen

IPC: G02F11333

CPC classification number: G02F1/13452 ,  G02F1/1309 ,  G02F2001/136263

Abstract: A liquid crystal display panel includes a first substrate, at least two first printed circuit boards, and at least one repair line. Each of the first printed circuit boards is utilized to output signals to a plurality of first conducting wires in parallel arranged on the first substrate. Additionally, the repair line has a first part located on the first substrate, a second part located on each of the first printed circuit boards, and a third part located on a connecting region between the first printed circuit boards.

公开(公告)号：US08962433B2

公开(公告)日：2015-02-24

申请号：US13494016

申请日：2012-06-12

Applicant: Chin-I Liao ,  Chin-Cheng Chien

Inventor： Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L21/336

CPC classification number: H01L29/7834 ,  H01L29/4966 ,  H01L29/66636 ,  H01L29/7848

Abstract: A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.

Abstract translation: MOS晶体管工艺包括以下步骤。 在基板上形成栅极结构。 在栅极结构旁边的衬底中形成源极/漏极。 在形成源极/漏极之后，（1）在栅极结构旁边的基板中形成至少一个凹部。 在凹部中形成外延结构。 （2）可以进行清洁处理以清洁栅极结构旁边的基板的表面。 在栅极结构旁边的衬底中形成外延结构。

公开(公告)号：US08921206B2

公开(公告)日：2014-12-30

申请号：US13308513

申请日：2011-11-30

Applicant: Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

Inventor： Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L21/36

CPC classification number: H01L29/6656 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.

Abstract translation: 首先，在半导体工艺中设置具有凹部的基板。 第二，在衬底中形成嵌入的SiGe层。 嵌入的SiGe层包括填充凹槽的外延SiGe材料。 然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。 接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。 之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。 前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

公开(公告)号：US08822284B2

公开(公告)日：2014-09-02

申请号：US13370231

申请日：2012-02-09

Applicant: Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/318 ,  H01L21/314

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

Abstract translation: 描述了制造FinFET的方法。 图案化半导体衬底以形成奇数鳍片。 间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。 然后在间隔件之间的基板上均匀形成翅片。 还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

公开(公告)号：US08716750B2

公开(公告)日：2014-05-06

申请号：US13189570

申请日：2011-07-25

Applicant: Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.

Abstract translation: 具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。 外延结构包括掺杂剂，具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料，并且第二晶格常数大于第一晶格常数。 未掺杂的帽层还包括第一半导体材料和第二半导体材料。 外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料至少包含第一浓度，第二浓度低于第一浓度。

公开(公告)号：US08647941B2

公开(公告)日：2014-02-11

申请号：US13211319

申请日：2011-08-17

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/8238

CPC classification number: H01L29/7846 ,  H01L21/76283 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.

Abstract translation: 形成半导体器件的方法包括以下步骤。 提供具有第一应变硅层的半导体衬底。 然后，形成诸如浅沟槽隔离（STI）的绝缘区域，其中绝缘区域的深度基本上大于第一应变硅层的深度。 随后，去除第一应变硅层，形成第二应变硅层以代替第一应变硅层。

公开(公告)号：US08519390B2

公开(公告)日：2013-08-27

申请号：US13189565

申请日：2011-07-25

Applicant: Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

IPC: H01L23/58

CPC classification number: H01L22/12 ,  H01L22/30

Abstract: A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.

Abstract translation: 使用X射线衍射（XRD）测量半导体合金的测试图案包括限定在晶片上的第N个区域和第N个区域，以及位于第一区域等等至第N区域的多个测试结构。 相同区域中的测试结构具有彼此相同的尺寸，并且不同区域中的测试结构具有彼此不同的尺寸。

公开(公告)号：US08497198B2

公开(公告)日：2013-07-30

申请号：US13243485

申请日：2011-09-23

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/4763 ,  H01L21/3205 ,  H01L21/336

CPC classification number: H01L29/66795

Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.

Abstract translation: 半导体工艺描述如下。 在基板上形成多个虚设图案。 在基板上共形形成掩模材料层，以覆盖虚设图案。 掩模材料层具有与虚拟图案不同的蚀刻速率。 除去掩模材料层的一部分，以便在每个虚设图案的各个侧壁上形成掩模层。 掩模层的上表面和每个虚拟图案的上表面基本上共面。 虚拟图案被去除。 使用掩模层作为掩模去除衬底的一部分，以便形成多个翅片结构和交替布置在衬底中的多个沟槽。 去除掩模层。