公开(公告)号：US11204826B2

公开(公告)日：2021-12-21

申请号：US16535787

申请日：2019-08-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hiroki Noguchi ,  Yu-Der Chih ,  Hsueh-Chih Yang ,  Randy Osborne ,  Win San Khwa

IPC分类号： G06F11/10 ,  G11C29/52 ,  G11C11/16

摘要： A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

公开(公告)号：US20210383867A1

公开(公告)日：2021-12-09

申请号：US17409341

申请日：2021-08-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC分类号： G11C14/00 ,  G11C11/419 ,  G11C11/16

摘要： Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US11152057B2

公开(公告)日：2021-10-19

申请号：US16507917

申请日：2019-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hidehiro Fujiwara ,  Cheng Chun Dai ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hiroki Noguchi

IPC分类号： G11C11/419 ,  G11C11/16

摘要： A static random access memory (SRAM) circuit can group the column bit lines in a memory array into subsets of bit lines, and a y-address signal input is provided for each subset of bit lines. Additionally or alternatively, each row in the array of memory cells is operably connected to multiple word lines.

公开(公告)号：US20210272647A1

公开(公告)日：2021-09-02

申请号：US17130250

申请日：2020-12-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/24 ,  G11C29/20

摘要： A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

公开(公告)号：US20210174854A1

公开(公告)日：2021-06-10

申请号：US16709622

申请日：2019-12-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Win-San Khwa ,  Hiroki Noguchi ,  Ku-Feng Lin

IPC分类号： G11C11/16 ,  H03M7/16 ,  H03K19/20

摘要： An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

公开(公告)号：US10943667B2

公开(公告)日：2021-03-09

申请号：US16657284

申请日：2019-10-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hiroki Noguchi ,  Wei-Chang Zhao

IPC分类号： G11C19/28 ,  G11C8/08 ,  G11C7/22 ,  G11C7/10

摘要： A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.

公开(公告)号：US20240296887A1

公开(公告)日：2024-09-05

申请号：US18662806

申请日：2024-05-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC分类号： G11C14/00 ,  G11C11/16 ,  G11C11/419

CPC分类号： G11C14/0081 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/419

摘要： Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US11962332B2

公开(公告)日：2024-04-16

申请号：US18165025

申请日：2023-02-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Win-San Khwa ,  Hiroki Noguchi ,  Ku-Feng Lin

IPC分类号： H03M7/00 ,  G11C11/16 ,  H03K19/20 ,  H03M7/16

CPC分类号： H03M7/16 ,  G11C11/1673 ,  H03K19/20

摘要： An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

公开(公告)号：US20240029791A1

公开(公告)日：2024-01-25

申请号：US18352127

申请日：2023-07-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hiroki Noguchi ,  Yu-Der Chih ,  Yih Wang

IPC分类号： G11C13/00 ,  G11C11/22 ,  G11C11/16

CPC分类号： G11C13/0069 ,  G11C11/2275 ,  G11C11/1675 ,  G11C2013/0092

摘要： A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

公开(公告)号：US20230147686A1

公开(公告)日：2023-05-11

申请号：US18149149

申请日：2023-01-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Perng-Fei Yuh ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Yih Wang

IPC分类号： G11C14/00 ,  G11C11/412 ,  G11C11/419 ,  G11C11/16 ,  G11C11/418

CPC分类号： G11C14/0081 ,  G11C11/412 ,  G11C11/419 ,  G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/418

摘要： A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.