公开(公告)号：US11855219B2

公开(公告)日：2023-12-26

申请号：US17509220

申请日：2021-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chi-Yuan Shih ,  Chi-Wen Liu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L23/29 ,  H01L23/31 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

公开(公告)号：US11798989B2

公开(公告)日：2023-10-24

申请号：US17805719

申请日：2022-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/06 ,  H01L21/82 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L21/3065

CPC classification number: H01L29/0673 ,  H01L21/3081 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/3065

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US11749603B2

公开(公告)日：2023-09-05

申请号：US17811649

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L31/062 ,  H01L31/113 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/3065 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/485 ,  H01L23/528 ,  H01L23/535 ,  H01L23/53266 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

公开(公告)号：US11652141B2

公开(公告)日：2023-05-16

申请号：US17656258

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L21/82 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L21/3065

CPC classification number: H01L29/0673 ,  H01L21/3081 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/3065

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US20220352329A1

公开(公告)日：2022-11-03

申请号：US17813110

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L27/088 ,  H01L29/06 ,  H01L29/45

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US20220344274A1

公开(公告)日：2022-10-27

申请号：US17811649

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/3065 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

公开(公告)号：US20200303258A1

公开(公告)日：2020-09-24

申请号：US16895345

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Ting-Hung Hsu ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762

Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

公开(公告)号：US10147603B2

公开(公告)日：2018-12-04

申请号：US15197004

申请日：2016-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  National Taiwan University

Inventor： Shih-Yen Lin ,  Chi-Wen Liu ,  Si-Chen Lee ,  Chong-Rong Wu ,  Kuan-Chao Chen

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66

Abstract: In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS2 layer. Source and drain electrodes are formed on the MoS2 layer. The MoS2 layer is treated with low-power oxygen plasma. A gate dielectric layer is formed on the MoS2 layer. A gate electrode is formed on the gate dielectric layer. An input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

公开(公告)号：US20180012962A1

公开(公告)日：2018-01-11

申请号：US15203674

申请日：2016-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ling-Yen Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/24 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/785

Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.

公开(公告)号：US09647122B2

公开(公告)日：2017-05-09

申请号：US15154982

申请日：2016-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Cheng-Chien Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/36 ,  H01L29/06 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.