公开(公告)号：US11587929B2

公开(公告)日：2023-02-21

申请号：US16880230

申请日：2020-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Taehyun An ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  G11C5/06

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

公开(公告)号：US20220293420A1

公开(公告)日：2022-09-15

申请号：US17680996

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

公开(公告)号：US11270885B2

公开(公告)日：2022-03-08

申请号：US16776948

申请日：2020-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

公开(公告)号：US11133315B2

公开(公告)日：2021-09-28

申请号：US16564071

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L29/49

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device comprises a substrate having a trench, a gate dielectric layer covering a surface of the trench, a gate electrode filling a lower portion of the trench, a capping pattern on the gate electrode in the trench, and a work function control pattern between the gate electrode and the capping pattern in the trench. The gate dielectric layer comprises a first segment having a first thickness between the gate electrode and the trench and a second segment having a second thickness between the capping pattern and the trench. The second thickness is less than the first thickness.

公开(公告)号：US11088143B2

公开(公告)日：2021-08-10

申请号：US16896470

申请日：2020-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US11037930B2

公开(公告)日：2021-06-15

申请号：US16670232

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Huijung Kim ,  Sohyun Park ,  Jaehwan Cho ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a contact plug structure being adjacent to the bit line structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a capacitor electrically connected to the contact plug structure. The contact plug structure includes a lower contact plug, a metal silicide pattern, and an upper contact plug that are sequentially stacked on the substrate. The metal silicide pattern has an L-shaped cross section.

公开(公告)号：US10468350B2

公开(公告)日：2019-11-05

申请号：US15592860

申请日：2017-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US11929324B2

公开(公告)日：2024-03-12

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  G11C5/10 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L29/0649 ,  H01L29/4236 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20230380173A1

公开(公告)日：2023-11-23

申请号：US18101606

申请日：2023-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongjoo Ku ,  Keunnam Kim ,  Kiseok Lee

IPC: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H01L23/528 ,  G11C16/08 ,  G11C16/26

CPC classification number: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H01L23/5283 ,  G11C16/08 ,  G11C16/26

Abstract: A semiconductor memory device includes a semiconductor substrate, a peripheral circuit structure disposed on the semiconductor substrate, and a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells of the cell array structure includes a bit line extending in a first horizontal direction, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a first word line extending in a second horizontal direction crossing the first horizontal direction on the channel pattern, a first gate insulating pattern located between the channel pattern and the first word line, a landing pad connected to the vertical channel portion of the channel pattern, and a data storage pattern disposed on the landing pad.

公开(公告)号：US11805639B2

公开(公告)日：2023-10-31

申请号：US17372634

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euna Kim ,  Keunnam Kim ,  Kiseok Lee ,  Wooyoung Choi ,  Sunghee Han

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/528 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.