公开(公告)号：US20210210492A1

公开(公告)日：2021-07-08

申请号：US16806667

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Il HAN ,  Sunghee HAN ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

公开(公告)号：US20210005506A1

公开(公告)日：2021-01-07

申请号：US16722622

申请日：2019-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyujin KIM ,  Hui-Jung KIM ,  Junsoo KIM ,  Sangho LEE ,  Jae-Hwan CHO ,  Yoosang HWANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

公开(公告)号：US20200227418A1

公开(公告)日：2020-07-16

申请号：US16732925

申请日：2020-01-02

Applicant: Samsung Electronics Co., ltd.

Inventor： Hui-Jung KIM ,  Min Hee CHO ,  Junsoo KIM ,  Taehyun An ,  Dongsoo Woo ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.

公开(公告)号：US20190206983A1

公开(公告)日：2019-07-04

申请号：US16115690

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyung NAM ,  Bong-Soo KIM ,  Yoosang HWANG

IPC: H01L49/02 ,  H01L27/108 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213

Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.

公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20170294440A1

公开(公告)日：2017-10-12

申请号：US15631105

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Sohyun PARK ,  Bong-Soo KIM ,  Yoosang HWANG ,  Dong-Wan KIM ,  Junghoon HAN

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

公开(公告)号：US20170077102A1

公开(公告)日：2017-03-16

申请号：US15083819

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun KIM ,  Yongkwan KIM ,  Semyeong JANG ,  Jaehyoung CHOI ,  Yoosang HWANG ,  Bong-Soo KIM

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/45 ,  H01L23/522

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.

Abstract translation: 半导体器件包括衬底上的存储电极和被配置为耦合存储电极的一个或多个部分的一个或多个支撑器。 半导体器件可以包括平行于衬底的表面延伸的多个不相交的支撑体。 至少一个支撑件可以具有与存储电极的上表面基本上共面的上表面。 存储电极可以包括保形地覆盖存储电极的一个或多个表面和一个或多个支持者的电容器电介质层。 存储电极可以包括耦合在一起的上部和下部存储电极。 上下存储电极可以具有不同的水平宽度。

公开(公告)号：US20170069633A1

公开(公告)日：2017-03-09

申请号：US15148405

申请日：2016-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Sohyun PARK ,  Bong-Soo KIM ,  Yoosang HWANG ,  Dong-Wan KIM ,  Junghoon HAN

IPC: H01L27/108 ,  H01L21/027 ,  H01L49/02 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/311

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

Abstract translation: 一种形成半导体器件的方法包括在包括蚀刻停止层的基底上形成模制层和支撑层，在支撑层上形成掩模层，在掩模层上形成第一边缘阻挡层，通过 蚀刻掩模层，形成孔，在孔中形成下电极，在载体层上形成支持体掩模层，在载体掩模层上形成第二边缘阻挡层，通过图案化载体掩模层形成载体掩模图案 形成穿过支撑层的支撑件开口，去除模制层，在下电极上形成电容器电介质层和上电极，在上电极上形成层间绝缘层，并平坦化层间绝缘层。 孔穿过支撑层，模制层和蚀刻停止层。

公开(公告)号：US20150179574A1

公开(公告)日：2015-06-25

申请号：US14618837

申请日：2015-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jay-Bok CHOI ,  Jiyoung KIM ,  Hyun-Woo CHUNG ,  Sungkwan CHOI ,  Yoosang HWANG

IPC: H01L23/528 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10891 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.

Abstract translation: 根据制造半导体器件的方法，使用第一掩模图案来蚀刻第一器件隔离层和有源线或形成凹槽，其中将提供字线。 此后，通过使用第一掩模图案作为蚀刻掩模，以自对准方式蚀刻有源线。 结果，可以抑制掩模未对准的发生。

公开(公告)号：US20150001617A1

公开(公告)日：2015-01-01

申请号：US14488426

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik KIM ,  HyeongSun HONG ,  Yongchul OH ,  Yoosang HWANG

IPC: H01L27/105 ,  H01L23/538 ,  H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L27/1052 ,  H01L23/5386 ,  H01L27/088 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/515 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

Abstract translation: 制造半导体器件的方法可以包括在衬底中形成第一沟槽以限定鳍片图案并形成填充第一沟槽的较低区域的埋入电介质图案。 第一个沟槽并行延伸。 栅电介质层形成在第一沟槽的上内侧壁上，并且在包括栅极电介质层的衬底上形成填充第一沟槽的栅极导电层。 栅极导电层，栅极电介质层和鳍状图案被图案化以形成与第一沟槽交叉并限定有源支柱的第二沟槽。 还可以提供半导体器件。