公开(公告)号：US20240276710A1

公开(公告)日：2024-08-15

申请号：US18362998

申请日：2023-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon UHM ,  Min Hee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes: a substrate; a bit line above the substrate; a channel pattern on the bit line extending in a direction perpendicular to an upper surface of the bit line; a word line intersecting the bit line and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; an insulating pattern on the word line; and a landing pad connected to the channel pattern. The channel pattern includes first, second, and third channel patterns that are sequentially stacked, the first channel pattern is connected to the bit line, the second channel pattern is between the first channel pattern and the third channel pattern, the third channel pattern is connected to the landing pad, the first channel pattern and the third channel pattern include a crystalline oxide semiconductor material, and the second channel pattern includes an amorphous oxide semiconductor material.

公开(公告)号：US20240244831A1

公开(公告)日：2024-07-18

申请号：US18239268

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggeun SONG ,  Sanghoon UHM ,  Yongjin LEE ,  Min Hee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device includes a bit line extending in a first direction on a substrate. A first insulating pattern is disposed on the bit line. A channel pattern is disposed on an upper side of the bit line and a lateral side of the first insulating pattern. The channel pattern includes an oxide semiconductor material. A gate insulating pattern is disposed on the channel pattern. Word lines are disposed on the gate insulating pattern. A second insulating pattern is disposed on the word lines. A landing pad is disposed on the channel pattern. An interlayer insulating layer disposed between the bit line and the channel pattern.

公开(公告)号：US20210020781A1

公开(公告)日：2021-01-21

申请号：US16778114

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee CHO ,  Woo Bin SONG ,  Hyun Mog PARK ,  Min Woo SONG

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/04 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, an oxide semiconductor film on the substrate, a first gate structure on the oxide semiconductor film and a contact that is in contact with the oxide semiconductor film, the contact being disposed on a boundary surface with the oxide semiconductor film, and including a metal oxide film that includes a transition metal.

公开(公告)号：US20240371994A1

公开(公告)日：2024-11-07

申请号：US18775518

申请日：2024-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US20230055499A1

公开(公告)日：2023-02-23

申请号：US17805706

申请日：2022-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

公开(公告)号：US20220336672A1

公开(公告)日：2022-10-20

申请号：US17856202

申请日：2022-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee CHO ,  Woo Bin SONG ,  Hyun Mog PARK ,  Min Woo SONG

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/04 ,  H01L29/45

Abstract: A semiconductor device includes a substrate, an oxide semiconductor film on the substrate, a first gate structure on the oxide semiconductor film and a contact that is in contact with the oxide semiconductor film, the contact being disposed on a boundary surface with the oxide semiconductor film, and including a metal oxide film that includes a transition metal.

公开(公告)号：US20220102352A1

公开(公告)日：2022-03-31

申请号：US17241860

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Kyunghwan LEE ,  Dongoh KIM ,  Yongseok KIM ,  Hui-jung KIM ,  Min Hee CHO

IPC: H01L27/108

Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

公开(公告)号：US20220367721A1

公开(公告)日：2022-11-17

申请号：US17694903

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Kyeong JEONG ,  Min Tae RYU ,  Hyeon Joo SEUL ,  Sungwon YOO ,  Wonsok LEE ,  Min Hee CHO ,  Jae Seok HUR

IPC: H01L29/786

Abstract: Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

公开(公告)号：US20220223732A1

公开(公告)日：2022-07-14

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H01L27/108

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US20200227418A1

公开(公告)日：2020-07-16

申请号：US16732925

申请日：2020-01-02

Applicant: Samsung Electronics Co., ltd.

Inventor： Hui-Jung KIM ,  Min Hee CHO ,  Junsoo KIM ,  Taehyun An ,  Dongsoo Woo ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.