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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230157003A1

    公开(公告)日：2023-05-18

    申请号：US17828298

    申请日：2022-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Keunnam KIM ,  Yongseok KIM ,  Hui-Jung KIM ,  Min Hee CHO ,  Yoosang HWANG

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/10873 ,  H01L27/10897

    Abstract: A semiconductor memory device including a stack structure including layer groups that are vertically stacked on a substrate and including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a vertically extending bit line on one side of the stack structure, wherein the word line of each of the layer groups extends in a first direction parallel to a top surface of the substrate, the layer groups include first and second layer groups that are sequentially stacked, the channel layer is below the word line of the first layer group, the channel layer is above the word line of the second layer group, and the bit line includes a first protrusion portion connected to the channel layer of the first layer group; and a second protrusion portion connected to the channel layer of the second layer group.

    SEMICONDUCTOR MEMORY DEVICES
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190164985A1

    公开(公告)日：2019-05-30

    申请号：US16027887

    申请日：2018-07-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210125989A1

    公开(公告)日：2021-04-29

    申请号：US16986367

    申请日：2020-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joongchan SHIN ,  Changkyu KIM ,  Hui-Jung KIM ,  Iljae SHIN ,  Taehyun AN ,  Kiseok LEE ,  Eunju CHO ,  Hyungeun CHOI ,  Sung-Min PARK ,  Ahram LEE ,  Sangyeon HAN ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

    SEMICONDUCTOR MEMORY DEVICES
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200111793A1

    公开(公告)日：2020-04-09

    申请号：US16707019

    申请日：2019-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L49/02 ,  H01L27/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200013668A1

    公开(公告)日：2020-01-09

    申请号：US16577429

    申请日：2019-09-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byoungdeog CHOI ,  JungWoo SEO ,  Sangyeon HAN ,  Hyun-Woo CHUNG ,  Hongrae KIM ,  Yoosang HWANG

    IPC: H01L21/768 ,  H01L23/498 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

    Abstract: A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset.

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