公开(公告)号：US20150179574A1

公开(公告)日：2015-06-25

申请号：US14618837

申请日：2015-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jay-Bok CHOI ,  Jiyoung KIM ,  Hyun-Woo CHUNG ,  Sungkwan CHOI ,  Yoosang HWANG

IPC: H01L23/528 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10891 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.

Abstract translation: 根据制造半导体器件的方法，使用第一掩模图案来蚀刻第一器件隔离层和有源线或形成凹槽，其中将提供字线。 此后，通过使用第一掩模图案作为蚀刻掩模，以自对准方式蚀刻有源线。 结果，可以抑制掩模未对准的发生。

公开(公告)号：US20150055401A1

公开(公告)日：2015-02-26

申请号：US14537387

申请日：2014-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Yongchul OH ,  Dongsoo WOO ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  Sungkwan CHOI ,  Hyeongsun HONG ,  Yoosang HWANG

IPC: G11C11/4096 ,  G11C11/404 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Abstract translation: 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。