公开(公告)号：US20140291804A1

公开(公告)日：2014-10-02

申请号：US14077834

申请日：2013-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Un KIM ,  Yoo-Sang HWANG ,  Hyun-Woo CHUNG

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C11/4097 ,  G11C11/4099 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block.

Abstract translation: 半导体存储器件包括包括单元块，平衡块和感测块的衬底。 在单元块中形成多个单元位线。 在位线的侧面附近形成多个电池插头。 在单元位线和电池插头之间形成电池内隔板，空气间隔件和电池外隔板。 在平衡块中形成多个平衡位线。 在平衡位线的侧表面附近形成多个平衡塞。 在平衡位线和平衡插头之间形成平衡内部间隔件和平衡外部间隔件。 平衡位线和至少一些单元位线连接到感测块。

公开(公告)号：US20150179574A1

公开(公告)日：2015-06-25

申请号：US14618837

申请日：2015-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jay-Bok CHOI ,  Jiyoung KIM ,  Hyun-Woo CHUNG ,  Sungkwan CHOI ,  Yoosang HWANG

IPC: H01L23/528 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10891 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.

Abstract translation: 根据制造半导体器件的方法，使用第一掩模图案来蚀刻第一器件隔离层和有源线或形成凹槽，其中将提供字线。 此后，通过使用第一掩模图案作为蚀刻掩模，以自对准方式蚀刻有源线。 结果，可以抑制掩模未对准的发生。

公开(公告)号：US20150055401A1

公开(公告)日：2015-02-26

申请号：US14537387

申请日：2014-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Yongchul OH ,  Dongsoo WOO ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  Sungkwan CHOI ,  Hyeongsun HONG ,  Yoosang HWANG

IPC: G11C11/4096 ,  G11C11/404 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Abstract translation: 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US20210159113A1

公开(公告)日：2021-05-27

申请号：US17144226

申请日：2021-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungdeog CHOI ,  JungWoo SEO ,  Sangyeon HAN ,  Hyun-Woo CHUNG ,  Hongrae KIM ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L23/498 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.

公开(公告)号：US20200013668A1

公开(公告)日：2020-01-09

申请号：US16577429

申请日：2019-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungdeog CHOI ,  JungWoo SEO ,  Sangyeon HAN ,  Hyun-Woo CHUNG ,  Hongrae KIM ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L23/498 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset.