公开(公告)号：US20140291804A1

公开(公告)日：2014-10-02

申请号：US14077834

申请日：2013-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Un KIM ,  Yoo-Sang HWANG ,  Hyun-Woo CHUNG

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C11/4097 ,  G11C11/4099 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block.

Abstract translation: 半导体存储器件包括包括单元块，平衡块和感测块的衬底。 在单元块中形成多个单元位线。 在位线的侧面附近形成多个电池插头。 在单元位线和电池插头之间形成电池内隔板，空气间隔件和电池外隔板。 在平衡块中形成多个平衡位线。 在平衡位线的侧表面附近形成多个平衡塞。 在平衡位线和平衡插头之间形成平衡内部间隔件和平衡外部间隔件。 平衡位线和至少一些单元位线连接到感测块。

公开(公告)号：US20140264568A1

公开(公告)日：2014-09-18

申请号：US14191832

申请日：2014-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Soo KIM ,  Jong-Un KIM ,  Nam-Ho JEON

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894

Abstract: In a method of manufacturing a semiconductor device, a trench is formed by removing an upper portion of a substrate. A gate insulation layer pattern is formed on an inner wall of the trench. A gate electrode is formed on the gate insulation layer pattern. The gate electrode fills a lower portion of the trench. A capping layer is formed on the gate electrode and the gate insulation layer pattern. The capping layer is partially oxidized to form a first capping layer pattern and a second capping layer pattern. The first capping layer pattern is not oxidized, and the second capping layer pattern is oxidized. A third capping layer pattern is formed on the second capping layer pattern, the third capping layer pattern filling an upper portion of the trench.

Abstract translation: 在制造半导体器件的方法中，通过去除衬底的上部形成沟槽。 栅极绝缘层图案形成在沟槽的内壁上。 在栅极绝缘层图案上形成栅电极。 栅电极填充沟槽的下部。 在栅极电极和栅极绝缘层图案上形成覆盖层。 覆盖层被部分氧化以形成第一覆盖层图案和第二覆盖层图案。 第一盖层图案不被氧化，第二盖层图案被氧化。 第三覆盖层图案形成在第二覆盖层图案上，第三覆盖层图案填充沟槽的上部。

公开(公告)号：US20150179641A1

公开(公告)日：2015-06-25

申请号：US14472765

申请日：2014-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-IL HAN ,  Jong-Un KIM

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L21/762 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0649

Abstract: A semiconductor memory device including a substrate, a first element isolation film pattern, and a second element isolation film pattern. The substrate includes a first region and a second region. The first element isolation film pattern is in the first region and corresponds to a first active region. The second element isolation film pattern is in the second region and corresponds to a second active region. The first element isolation film pattern includes a first material and the second element isolation film pattern includes a second material different from the first material.

Abstract translation: 一种半导体存储器件，包括衬底，第一元件隔离膜图案和第二元件隔离膜图案。 衬底包括第一区域和第二区域。 第一元件隔离膜图案位于第一区域中并且对应于第一有源区域。 第二元件隔离膜图案在第二区域中并且对应于第二有源区域。 第一元件隔离膜图案包括第一材料，第二元件隔离膜图案包括与第一材料不同的第二材料。

公开(公告)号：US20150171214A1

公开(公告)日：2015-06-18

申请号：US14472571

申请日：2014-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-IL HAN ,  Jong-Un KIM ,  Jun-Soo KIM

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7827

Abstract: Provided is a semiconductor device, including a substrate including a device isolation layer and an active region isolated by the device isolation layer; a trench in the active region; a gate electrode filling at least a portion of the trench; a recess in the substrate at one side of the gate electrode, the recess overlapping a portion of the device isolation layer and the active region; and a lower contact plug filling the recess.

Abstract translation: 提供一种半导体器件，包括：衬底，其包括器件隔离层和由器件隔离层隔离的有源区; 活跃区域的沟槽; 填充所述沟槽的至少一部分的栅电极; 在栅电极的一侧的衬底中的凹部，凹部与器件隔离层的一部分和有源区重叠; 以及填充凹部的下接触塞。