公开(公告)号：US20150228573A1

公开(公告)日：2015-08-13

申请号：US14457185

申请日：2014-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min PARK ,  Yoo-Sang HWANG

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/538 ,  H01L23/535

CPC classification number: H01L23/5386 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region. An interlayer insulating layer is disposed on the semiconductor substrate. A lower contact plug passing through the interlayer insulating layer and electrically connected to the contact region is disposed. An interconnection structure is disposed on the interlayer insulating layer. An adjacent interconnection spaced apart from the interconnection structure is disposed on the interlayer insulating layer. A bottom surface of the interconnection structure includes a first part overlapping a part of an upper surface of the lower contact plug, and a second part overlapping the interlayer insulating layer.

Abstract translation: 提供一种半导体器件。 半导体器件包括具有接触区域的半导体衬底。 层间绝缘层设置在半导体衬底上。 设置穿过层间绝缘层并电连接到接触区域的下接触插塞。 互连结构设置在层间绝缘层上。 与互连结构间隔开的相邻互连设置在层间绝缘层上。 互连结构的底表面包括与下接触插塞的上表面的一部分重叠的第一部分和与层间绝缘层重叠的第二部分。

公开(公告)号：US20170005097A1

公开(公告)日：2017-01-05

申请号：US15196273

申请日：2016-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Jung KIM ,  Bong-Soo KIM ,  Yong-Kwan KIM ,  Sung-Hee HAN ,  Yoo-Sang HWANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.

Abstract translation: 一种半导体器件，包括限定在半导体衬底中的有源区; 在所述半导体衬底上的第一接触插塞，所述第一接触插塞连接到所述有源区; 所述半导体衬底上的位线，所述位线与所述第一接触插塞相邻; 在所述第一接触插塞和所述位线之间的第一气隙间隔件; 第一接触塞上的着陆垫; 位线上的阻挡绝缘层; 以及在所述第一气隙间隔件上的气隙盖层，所述气隙盖层与所述第一气隙间隔件垂直重叠，所述气隙盖层位于所述阻挡绝缘层和所述着陆焊盘之间，所述阻挡绝缘层的上表面 处于与着陆垫的上表面相同或更高的高度。

公开(公告)号：US20150111360A1

公开(公告)日：2015-04-23

申请号：US14515874

申请日：2014-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Wan KIM ,  Byeung-Chul KIM ,  Bong-Soo KIM ,  Je-Min PARK ,  Yoo-Sang HWANG

IPC: H01L27/108 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/3205 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/10855 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91 ,  H01L29/4236

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive layer on a substrate, partially removing the first conductive layer and an upper portion of the substrate to form a recess, forming a second conductive layer pattern to fill the recess, forming a third conductive layer on the second conductive layer pattern and the first conductive layer, and patterning the third conductive layer and the second conductive layer pattern to form a bit line structure and a bit line contact, respectively.

Abstract translation: 制造半导体器件的方法包括在衬底上形成第一导电层，部分地去除第一导电层和衬底的上部以形成凹陷，形成第二导电层图案以填充凹部，形成第三导电 在第二导电层图案和第一导电层上的层，并且分别构图第三导电层和第二导电层图案以形成位线结构和位线接触。

公开(公告)号：US20210020641A1

公开(公告)日：2021-01-21

申请号：US17060026

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Seok LEE ,  Bomg-Soo KIM ,  Ji-Young KIM ,  Sung-Hee HAN ,  Yoo-Sang HWANG

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/764

Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

公开(公告)号：US20140291804A1

公开(公告)日：2014-10-02

申请号：US14077834

申请日：2013-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Un KIM ,  Yoo-Sang HWANG ,  Hyun-Woo CHUNG

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C11/4097 ,  G11C11/4099 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block.

Abstract translation: 半导体存储器件包括包括单元块，平衡块和感测块的衬底。 在单元块中形成多个单元位线。 在位线的侧面附近形成多个电池插头。 在单元位线和电池插头之间形成电池内隔板，空气间隔件和电池外隔板。 在平衡块中形成多个平衡位线。 在平衡位线的侧表面附近形成多个平衡塞。 在平衡位线和平衡插头之间形成平衡内部间隔件和平衡外部间隔件。 平衡位线和至少一些单元位线连接到感测块。

公开(公告)号：US20140154882A1

公开(公告)日：2014-06-05

申请号：US14097786

申请日：2013-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik KIM ,  Ho-In RYU ,  Nak-Jin SON ,  Yoo-Sang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成器件隔离层图案以形成有源区，所述有源区包括位于有源区的中心p处的第一接触形成区和第二接触形成区 所述有源区，在所述基板上形成绝缘层和第一导电层，在所述第一导电层上形成具有隔离形状的掩模图案，蚀刻所述第一导电层和所述绝缘层，以暴露所述第一触点形成的有源区 通过使用掩模图案形成柱状结构之间的开口部分，在开口中形成第二导电层，图案化第二导电层和第一预导电层图案，以形成与第一接触形成区域接触的布线结构和 具有延长的线形。