公开(公告)号：US20130248980A1

公开(公告)日：2013-09-26

申请号：US13775586

申请日：2013-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Uk HAN ,  Jae-Hoon LEE ,  Jun-Su KIM ,  Satoru YAMADA ,  Jin-Seong LEE ,  Nam-Ho JEON

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L27/108 ,  H01L27/11

Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.

Abstract translation: 根据本发明构思的示例性实施例，一种无电容器存储器件包括：无电容器存储器单元，其在衬底上包括位线; 读取晶体管和写入晶体管。 读取晶体管可以包括在位线上沿垂直方向堆叠的第一至第三杂质层。 第一和第三层可以是第一导电类型，并且第二杂质层可以是不同于第一导电类型的第二导电类型。 写入晶体管可以包括在基板上沿垂直方向堆叠的源极层，主体层和漏极层，以及与主体层的侧表面相邻的栅极线。 栅极线可以与主体层的侧表面间隔开。 源极层可以与第二杂质层的侧表面相邻。

公开(公告)号：US20140264568A1

公开(公告)日：2014-09-18

申请号：US14191832

申请日：2014-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Soo KIM ,  Jong-Un KIM ,  Nam-Ho JEON

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894

Abstract: In a method of manufacturing a semiconductor device, a trench is formed by removing an upper portion of a substrate. A gate insulation layer pattern is formed on an inner wall of the trench. A gate electrode is formed on the gate insulation layer pattern. The gate electrode fills a lower portion of the trench. A capping layer is formed on the gate electrode and the gate insulation layer pattern. The capping layer is partially oxidized to form a first capping layer pattern and a second capping layer pattern. The first capping layer pattern is not oxidized, and the second capping layer pattern is oxidized. A third capping layer pattern is formed on the second capping layer pattern, the third capping layer pattern filling an upper portion of the trench.

Abstract translation: 在制造半导体器件的方法中，通过去除衬底的上部形成沟槽。 栅极绝缘层图案形成在沟槽的内壁上。 在栅极绝缘层图案上形成栅电极。 栅电极填充沟槽的下部。 在栅极电极和栅极绝缘层图案上形成覆盖层。 覆盖层被部分氧化以形成第一覆盖层图案和第二覆盖层图案。 第一盖层图案不被氧化，第二盖层图案被氧化。 第三覆盖层图案形成在第二覆盖层图案上，第三覆盖层图案填充沟槽的上部。