公开(公告)号：US20140264568A1

公开(公告)日：2014-09-18

申请号：US14191832

申请日：2014-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Soo KIM ,  Jong-Un KIM ,  Nam-Ho JEON

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894

Abstract: In a method of manufacturing a semiconductor device, a trench is formed by removing an upper portion of a substrate. A gate insulation layer pattern is formed on an inner wall of the trench. A gate electrode is formed on the gate insulation layer pattern. The gate electrode fills a lower portion of the trench. A capping layer is formed on the gate electrode and the gate insulation layer pattern. The capping layer is partially oxidized to form a first capping layer pattern and a second capping layer pattern. The first capping layer pattern is not oxidized, and the second capping layer pattern is oxidized. A third capping layer pattern is formed on the second capping layer pattern, the third capping layer pattern filling an upper portion of the trench.

Abstract translation: 在制造半导体器件的方法中，通过去除衬底的上部形成沟槽。 栅极绝缘层图案形成在沟槽的内壁上。 在栅极绝缘层图案上形成栅电极。 栅电极填充沟槽的下部。 在栅极电极和栅极绝缘层图案上形成覆盖层。 覆盖层被部分氧化以形成第一覆盖层图案和第二覆盖层图案。 第一盖层图案不被氧化，第二盖层图案被氧化。 第三覆盖层图案形成在第二覆盖层图案上，第三覆盖层图案填充沟槽的上部。

公开(公告)号：US20150171214A1

公开(公告)日：2015-06-18

申请号：US14472571

申请日：2014-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-IL HAN ,  Jong-Un KIM ,  Jun-Soo KIM

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7827

Abstract: Provided is a semiconductor device, including a substrate including a device isolation layer and an active region isolated by the device isolation layer; a trench in the active region; a gate electrode filling at least a portion of the trench; a recess in the substrate at one side of the gate electrode, the recess overlapping a portion of the device isolation layer and the active region; and a lower contact plug filling the recess.

Abstract translation: 提供一种半导体器件，包括：衬底，其包括器件隔离层和由器件隔离层隔离的有源区; 活跃区域的沟槽; 填充所述沟槽的至少一部分的栅电极; 在栅电极的一侧的衬底中的凹部，凹部与器件隔离层的一部分和有源区重叠; 以及填充凹部的下接触塞。