公开(公告)号：US20150001617A1

公开(公告)日：2015-01-01

申请号：US14488426

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik KIM ,  HyeongSun HONG ,  Yongchul OH ,  Yoosang HWANG

IPC: H01L27/105 ,  H01L23/538 ,  H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L27/1052 ,  H01L23/5386 ,  H01L27/088 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/515 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

Abstract translation: 制造半导体器件的方法可以包括在衬底中形成第一沟槽以限定鳍片图案并形成填充第一沟槽的较低区域的埋入电介质图案。 第一个沟槽并行延伸。 栅电介质层形成在第一沟槽的上内侧壁上，并且在包括栅极电介质层的衬底上形成填充第一沟槽的栅极导电层。 栅极导电层，栅极电介质层和鳍状图案被图案化以形成与第一沟槽交叉并限定有源支柱的第二沟槽。 还可以提供半导体器件。

公开(公告)号：US20170200609A1

公开(公告)日：2017-07-13

申请号：US15402545

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik KIM ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L27/11531 ,  H01L27/11575

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

公开(公告)号：US20190333918A1

公开(公告)日：2019-10-31

申请号：US16509820

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik KIM ,  SEMYEONG JANG ,  JEMIN PARK ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/792 ,  H01L21/71

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US20180301459A1

公开(公告)日：2018-10-18

申请号：US15952350

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Daeik KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Semyeong JANG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02 ,  B08B7/00

Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.