公开(公告)号：US20180331046A1

公开(公告)日：2018-11-15

申请号：US16026937

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Sooho SHIN ,  Juik LEE ,  Jun Ho LEE ,  Kwangmin KIM ,  Ilyoung MOON ,  Jemin PARK ,  Bumseok SEO ,  Chan-Sic YOON ,  Hoin LEE

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20190287977A1

公开(公告)日：2019-09-19

申请号：US16419947

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20180301459A1

公开(公告)日：2018-10-18

申请号：US15952350

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Daeik KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Semyeong JANG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02 ,  B08B7/00

Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

公开(公告)号：US20210408008A1

公开(公告)日：2021-12-30

申请号：US17471824

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L27/24

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20190221475A1

公开(公告)日：2019-07-18

申请号：US16106266

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok HONG ,  Kiseok LEE ,  Jemin PARK ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.

公开(公告)号：US20150340284A1

公开(公告)日：2015-11-26

申请号：US14569980

申请日：2014-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Yong Kwan KIM ,  Jemin PARK ,  Semyeong JANG ,  Sangyeon HAN ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L27/1288 ,  H01L21/7688 ,  H01L27/10814 ,  H01L27/10891

Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.

Abstract translation: 本发明构思提供了制造半导体器件的方法。 该方法可以包括提供衬底，在衬底上堆叠导电层和下掩模层，在下掩模层上形成各自具有岛状的多个硬掩模层，形成具有岛形的多个上掩模图案，其布置成 暴露下掩模层的部分，蚀刻下掩模层的暴露部分以暴露导电层的部分，并且蚀刻导电层的暴露部分以形成多个接触孔，每个接触孔暴露衬底的一部分。