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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210335790A1

    公开(公告)日：2021-10-28

    申请号：US17371452

    申请日：2021-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungwoo SONG ,  Kwangmin KIM ,  Jun Ho LEE ,  Hyuckjin KANG ,  Yong Kwan KIM ,  Sangyeon HAN ,  Seguen PARK

    IPC: H01L27/108 ,  H01L29/06 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
    3.
    发明申请
    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20150340284A1

    公开(公告)日：2015-11-26

    申请号：US14569980

    申请日：2014-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung KIM ,  Yong Kwan KIM ,  Jemin PARK ,  Semyeong JANG ,  Sangyeon HAN ,  Yoosang HWANG

    IPC: H01L21/768 ,  H01L29/66

    CPC classification number: H01L27/1288 ,  H01L21/7688 ,  H01L27/10814 ,  H01L27/10891

    Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.

    Abstract translation: 本发明构思提供了制造半导体器件的方法。 该方法可以包括提供衬底，在衬底上堆叠导电层和下掩模层，在下掩模层上形成各自具有岛状的多个硬掩模层，形成具有岛形的多个上掩模图案，其布置成 暴露下掩模层的部分，蚀刻下掩模层的暴露部分以暴露导电层的部分，并且蚀刻导电层的暴露部分以形成多个接触孔，每个接触孔暴露衬底的一部分。

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