公开(公告)号：US20210193656A1

公开(公告)日：2021-06-24

申请号：US17177824

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US10923602B2

公开(公告)日：2021-02-16

申请号：US16532645

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung Kim ,  Dong-Soo Lee ,  Sang-Yong Kim ,  Jin-Kyu Jang ,  Won-Keun Chung ,  Sang-Jin Hyun

IPC: H01L29/792 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/786 ,  H01L27/088

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

公开(公告)号：US10283600B2

公开(公告)日：2019-05-07

申请号：US15871628

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Gon Lee ,  Ryuji Tomita ,  Chul-Sung Kim ,  Sang-Jin Hyun

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.

公开(公告)号：US10115797B2

公开(公告)日：2018-10-30

申请号：US15059673

申请日：2016-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Sang-Jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/28

Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.

公开(公告)号：US20170365555A1

公开(公告)日：2017-12-21

申请号：US15389856

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hun Choi ,  Jeong-Ik Kim ,  Chul-Sung Kim ,  Jae-Eun Lee ,  Sang-Jin Hyun

IPC: H01L23/535 ,  H01L23/532 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

Abstract: Semiconductor devices may include a structure on a substrate, an insulating interlayer, a metal silicide pattern, a first barrier pattern, a second barrier pattern and a metal pattern. The structure may include silicon. The insulating interlayer may include a contact hole exposing a surface of the structure. The metal silicide pattern may be in a lower portion of the contact hole, and the metal silicide pattern may directly contact the exposed surface of the structure. The first barrier pattern may directly contact an upper surface of the metal silicide pattern and a sidewall of the contact hole. The first barrier pattern may include a metal nitride. The second barrier pattern may be formed on the first barrier pattern. The second barrier pattern may include a metal nitride. The metal pattern may be formed on the second barrier pattern. The metal pattern may be in the contact hole.

公开(公告)号：US09543300B2

公开(公告)日：2017-01-10

申请号：US15054571

申请日：2016-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/092 ,  H01L23/485 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/08 ,  H01L29/94

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

Abstract translation: 提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。 半导体衬底的第一和第二区域可以具有不同的导电类型。 第一和第二互连结构可以设置在半导体衬底上。 第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。 半导体器件可以设置在半导体模块中。

公开(公告)号：US20160380050A1

公开(公告)日：2016-12-29

申请号：US15137946

申请日：2016-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Young Kwak ,  Kyung-Seok Oh ,  Seung-Jae Lee ,  Sang-Jin Hyun

IPC: H01L29/06 ,  H01L21/31 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/31 ,  H01L21/823431 ,  H01L27/0886

Abstract: A semiconductor device is provided as follows. A first fin-type pattern is disposed on a substrate. A first field insulating film is adjacent to a sidewall of the first fin-type pattern. A second field insulating film is adjacent to a sidewall of the first field insulating film. The first field insulating film is interposed between the first fin-type pattern and the second field insulating film. The second field insulating film comprises a first region and a second region. The first region is closer to the sidewall of the first field insulating film. A height from a bottom of the second field insulating film to an upper surface of the second region is larger than a height from the bottom of the second field insulating film to an upper surface of the first region.

Abstract translation: 如下提供半导体器件。 第一鳍型图案设置在基板上。 第一场绝缘膜与第一鳍型图案的侧壁相邻。 第二场绝缘膜与第一场绝缘膜的侧壁相邻。 第一场绝缘膜介于第一鳍型和第二场绝缘膜之间。 第二场绝缘膜包括第一区域和第二区域。 第一区域更靠近第一场绝缘膜的侧壁。 从第二场绝缘膜的底部到第二区域的上表面的高度大于从第二场绝缘膜的底部到第一区域的上表面的高度。