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    SEMICONDUCTOR MEMORY DEVICE
    32.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250142806A1

    公开(公告)日：2025-05-01

    申请号：US19003119

    申请日：2024-12-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Ilgweon KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Jaeho HONG

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line at a first end of the semiconductor pattern, and a capacitor structure at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

    THREE DIMENSIONAL NON-VOLATILE MEMORY DEVICE
    34.
    发明公开
    THREE DIMENSIONAL NON-VOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20240306398A1

    公开(公告)日：2024-09-12

    申请号：US18594350

    申请日：2024-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongseok KIM ,  Yukio HAYAKAWA ,  Minjun LEE ,  Bongyong LEE ,  Siyeon CHO

    IPC: H10B53/30 ,  H10B53/20

    CPC classification number: H10B53/30 ,  H10B53/20

    Abstract: A three-dimensional non-volatile memory device includes a plurality of horizontal word lines spaced apart from each other in a vertical direction, a pillar gate electrode buried in a first channel hole that passes through the horizontal word lines in the vertical direction, and a first dielectric layer disposed between the pillar gate electrode and the horizontal word lines in a cross section. The pillar gate electrode, the first dielectric layer, and the horizontal word lines correspond to memory cells including a plurality of variable capacitors spaced apart from each other in a vertical direction. The memory device further includes a selection transistor on the pillar gate electrode and the horizontal word lines and connected to one end of the pillar gate electrode, and a storage transistor under the pillar gate electrode and the horizontal word lines and connected to another end of the pillar gate electrode.

    STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME
    35.
    发明公开
    STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240170072A1

    公开(公告)日：2024-05-23

    申请号：US18510074

    申请日：2023-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suhwan LIM ,  Kyunghwan LEE ,  Yongseok KIM

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/32

    CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/32

    Abstract: A storage device capable of performing erase operations in units smaller than blocks may include nonvolatile memory, and processing circuitry configured to, apply an erase voltage to a first bit line of the plurality of bit lines of at least one memory block of the plurality of memory blocks, apply an erase prohibition voltage to a second bit line of the plurality of bit lines, the erase prohibition voltage having a voltage level lower than a voltage level of the erase voltage, and float the common source line to cause an erasure of data stored in at least one first memory cell included in at least one first cell string connected to the first bit line by floating the common source line, and preserve data stored in at least one second memory cell included in at least one second cell string connected to the second bit line.

    MEMORY DEVICES
    36.
    发明公开
    MEMORY DEVICES 审中-公开

    公开(公告)号：US20230371270A1

    公开(公告)日：2023-11-16

    申请号：US18315181

    申请日：2023-05-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Kiheun LEE ,  Daewon HA

    IPC: H10B51/30 ,  H10B51/10 ,  H01L21/28

    CPC classification number: H10B51/30 ,  H10B51/10 ,  H01L29/40111

    Abstract: A memory device may include a channel region, a conductive electrode disposed on the channel region, and a data storage structure disposed between the channel region and the conductive electrode. The data storage structure includes a first dielectric layer and a second dielectric layer disposed on the first dielectric layer, the second dielectric layer includes a ferroelectric region and a barrier dielectric region on the ferroelectric region, the ferroelectric region includes a first material, and the barrier dielectric region includes a second material formed by nitriding or oxidizing the first material.

    SEMICONDUCTOR MEMORY DEVICE
    37.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230328950A1

    公开(公告)日：2023-10-12

    申请号：US18175445

    申请日：2023-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjun LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Mintae RYU ,  Yongjin LEE

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A semiconductor memory device includes a plurality of memory cells arranged on a substrate. Each of the plurality of memory cells may include a first transistor on the substrate and a second transistor on the first transistor. The first transistor may include a first channel region between a first source region and a first drain region, a first gate electrode, and a first gate insulating layer. The second transistor may include a pillar structure having a second drain region, a second channel region and a second source region sequentially stacked on the first gate electrode, a second gate electrode on one side of the second channel region, and a second gate insulating layer between the second channel region and the second gate electrode. The second drain region and the second source region may have a first conductivity type impurity region and a second conductivity type impurity region, respectively.

    SEMICONDUCTOR DEVICES
    38.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220199793A1

    公开(公告)日：2022-06-23

    申请号：US17443553

    申请日：2021-07-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Ilgweon KIM ,  Seokhan PARK ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L23/482

    Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities

    SEMICONDUCTOR MEMORY DEVICE
    39.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220102352A1

    公开(公告)日：2022-03-31

    申请号：US17241860

    申请日：2021-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Kyunghwan LEE ,  Dongoh KIM ,  Yongseok KIM ,  Hui-jung KIM ,  Min Hee CHO

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

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