公开(公告)号：US20240049472A1

公开(公告)日：2024-02-08

申请号：US18208943

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiheun LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Daewon HA

IPC: H10B51/20 ,  H10B51/10 ,  H01L29/78 ,  H01L29/51 ,  H01L29/18

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/18

Abstract: A ferroelectric memory device includes a channel layer, a gate insulation layer on the channel layer, and a gate electrode layer on the gate insulation layer. The gate insulation layer includes a ferroelectric inductive layer and a ferroelectric stack structure on the ferroelectric inductive layer, and the ferroelectric stack structure is stacked in an order or reverse order of a ferroelectric layer and a non-ferroelectric layer.

公开(公告)号：US20240276733A1

公开(公告)日：2024-08-15

申请号：US18405361

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Sanghyun PARK ,  Kiheun LEE ,  Sangwoo HAN

IPC: H10B51/30 ,  H10B51/20

CPC classification number: H10B51/30 ,  H10B51/20

Abstract: A semiconductor memory device includes a substrate, a semiconductor pattern on the substrate and including a source region having a first conductivity type, a drain region having a second conductivity type, and an intrinsic region between the source region and the drain region, first and second gate electrodes on the intrinsic region, a ferroelectric pattern between the intrinsic region and the first and second gate electrodes, and a gate dielectric pattern between the ferroelectric pattern and the intrinsic region.

公开(公告)号：US20230371270A1

公开(公告)日：2023-11-16

申请号：US18315181

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Kiheun LEE ,  Daewon HA

IPC: H10B51/30 ,  H10B51/10 ,  H01L21/28

CPC classification number: H10B51/30 ,  H10B51/10 ,  H01L29/40111

Abstract: A memory device may include a channel region, a conductive electrode disposed on the channel region, and a data storage structure disposed between the channel region and the conductive electrode. The data storage structure includes a first dielectric layer and a second dielectric layer disposed on the first dielectric layer, the second dielectric layer includes a ferroelectric region and a barrier dielectric region on the ferroelectric region, the ferroelectric region includes a first material, and the barrier dielectric region includes a second material formed by nitriding or oxidizing the first material.