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公开(公告)号：US20210358913A1
公开(公告)日：2021-11-18
申请号：US17092593
申请日：2020-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Huijung KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
IPC: H01L27/102 , H01L29/74
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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公开(公告)号：US20220352170A1
公开(公告)日：2022-11-03
申请号：US17725069
申请日：2022-04-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Ilgweon KIM , Hyeoungwon SEO , Sungwon YOO , Jaeho HONG
IPC: H01L27/108
Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.
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公开(公告)号：US20220216239A1
公开(公告)日：2022-07-07
申请号：US17503713
申请日：2021-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwon YOO , Yongseok KIM , Ilgweon KIM , Hyuncheol KIM , Hyeoungwon SEO , Kyunghwan LEE , Jaeho HONG
IPC: H01L27/12 , H01L27/13 , H01L25/065 , H01L25/18 , H01L21/84
Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.
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公开(公告)号：US20220029095A1
公开(公告)日：2022-01-27
申请号：US17192093
申请日：2021-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Hyeoungwon SEO , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.
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公开(公告)号：US20250113590A1
公开(公告)日：2025-04-03
申请号：US18976522
申请日：2024-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Huijung KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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Patent Agency Ranking
公开(公告)号：US20220028859A1
公开(公告)日：2022-01-27
申请号：US17191308
申请日：2021-03-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeho HONG , Kyunghwan Lee , Hyuncheol Kim , Huijung Kim , Hyunmog Park , Kiseok Lee , Minhee Cho
IPC: H01L27/108 , G11C5/06 , H01L29/24
Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.
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公开(公告)号：US20210225842A1
公开(公告)日：2021-07-22
申请号：US16999378
申请日：2020-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
IPC: H01L27/102 , H01L29/24
Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.
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公开(公告)号：US20250142806A1
公开(公告)日：2025-05-01
申请号：US19003119
申请日：2024-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Ilgweon KIM , Hyeoungwon SEO , Sungwon YOO , Jaeho HONG
IPC: H10B12/00
Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line at a first end of the semiconductor pattern, and a capacitor structure at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.
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公开(公告)号：US20220199793A1
公开(公告)日：2022-06-23
申请号：US17443553
申请日：2021-07-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol KIM , Yongseok KIM , Ilgweon KIM , Seokhan PARK , Kyunghwan LEE , Jaeho HONG
IPC: H01L29/423 , H01L29/66 , H01L29/78 , H01L23/482
Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities
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公开(公告)号：US20210359200A1
公开(公告)日：2021-11-18
申请号：US17110524
申请日：2020-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Kohji KANAMORI , Unghwan PI , Hyuncheol KIM , Sungwon YOO , Jaeho HONG
Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.
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