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公开(公告)号：US20240324221A1
公开(公告)日：2024-09-26
申请号：US18612110
申请日：2024-03-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Seogoo Kang , Kyungdong Kim , Seunghyun Lee , Jeehoon Han
IPC: H10B43/27 , G11C5/06 , G11C16/04 , G11C16/08 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40 , H10B80/00
CPC classification number: H10B43/27 , G11C5/063 , G11C16/0483 , G11C16/08 , H01L23/5283 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40 , H10B80/00 , H01L2225/06506
Abstract: A memory device is provided. The memory device includes a first cell array stack including first gate electrodes, a first channel structure, and first pad portions respectively connected to the first gate electrodes and having a step shape, a second cell array stack disposed on the first cell array stack and including second gate electrodes, a second channel structure, and second pad portions respectively connected to the second gate electrodes and having a step shape, wherein the second pad portions overlap the first pad portions in the first direction, and a vertical contact passing through any one of the first pad portions, first extension portions below the any one of the first pad portions, any one of the second pad portions, and second extension portions below the any one of the second pad portions, to extend in the first direction.
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公开(公告)号：US20240306389A1
公开(公告)日：2024-09-12
申请号：US18591486
申请日：2024-02-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/27 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40 , G11C16/08
Abstract: A memory device includes a first bit line pad and a second bit line pad on a substrate and separated from each other in a first horizontal direction, a plurality of horizontal channel areas extending parallel in the first horizontal direction between the first bit line pad and the second bit line pad, and alternately connected to the first bit line pad and the second bit line pad at first end portions of the plurality of horizontal channel areas, a plurality of common source plugs connected to the second end portions of the plurality of horizontal channel areas opposite to the first end portions, and a plurality of gate plugs extending in a vertical direction and disposed between the plurality of horizontal channel areas, and respectively having end portions in a second horizontal direction perpendicular to the first horizontal direction in contact with the plurality of horizontal channel areas.
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公开(公告)号：US12022658B2
公开(公告)日：2024-06-25
申请号：US18356064
申请日：2023-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
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公开(公告)号：US11974438B2
公开(公告)日：2024-04-30
申请号：US17903315
申请日：2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Haemin Lee , Jongwon Kim , Shinhwan Kang , Kohji Kanamori , Jeehoon Han
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
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公开(公告)号：US20240121957A1
公开(公告)日：2024-04-11
申请号：US18240017
申请日：2023-08-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myunghoon Han , Sehee Jang , Hyunho Kim , Jeehoon Han
CPC classification number: H10B43/27 , H01L23/562 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35
Abstract: A semiconductor device includes a gate electrode structure, a memory channel structure, a first division pattern, and first support patterns. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The memory channel structure extends through the gate electrode structure on the substrate. The first division pattern is formed on a sidewall of the gate electrode structure in a third direction parallel to the upper surface of the substrate and crossing the second direction, and extends in the second direction. The first support patterns are spaced apart from each other in the second direction on the first division pattern, and each of the first support patterns includes a conductive material.
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Patent Agency Ranking
公开(公告)号：US20240105604A1
公开(公告)日：2024-03-28
申请号：US18526208
申请日：2023-12-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Hun Lee , Seokjung Yun , Chang-Sup Lee , Seong Soon Cho , Jeehoon Han
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H10B41/20 , H10B41/27 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/35 , H10B43/50
CPC classification number: H01L23/5283 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H10B41/20 , H10B41/27 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/35 , H10B43/50
Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.
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公开(公告)号：US20230371260A1
公开(公告)日：2023-11-16
申请号：US18356064
申请日：2023-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
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公开(公告)号：US11778834B2
公开(公告)日：2023-10-03
申请号：US17983024
申请日：2022-11-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
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39.发明授权公开(公告)号：US11374017B2
公开(公告)日：2022-06-28
申请号：US16842055
申请日：2020-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Seogoo Kang , Jongseon Ahn , Jeehoon Han
IPC: H01L27/1157 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/11565 , H01L27/11573 , H01L29/49 , H01L21/28 , H01L27/11519 , H01L27/11582
Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.
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40.发明申请公开(公告)号：US20210091093A1
公开(公告)日：2021-03-25
申请号：US16842055
申请日：2020-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Seogoo Kang , Jongseon Ahn , Jeehoon Han
IPC: H01L27/1157 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573 , H01L29/49 , H01L21/28 , H01L27/11519 , H01L27/11565
Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.
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