公开(公告)号：US20150050785A1

公开(公告)日：2015-02-19

申请号：US14496225

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L21/8238 ,  H01L21/84 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在具体示例中，形成CMOS器件的方法包括在晶片的延伸层上形成第一层，在第一层的一部分上形成第一栅极，以及形成靠近延伸层的扩张区域。 该方法还包括去除第一栅极的一部分以产生空腔并去除第一层的一部分以将空腔延伸到延伸层。

公开(公告)号：US20140264485A1

公开(公告)日：2014-09-18

申请号：US13834594

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L29/66 ,  G06F17/50 ,  H01L29/78

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括鳍，其包括具有第一掺杂浓度的第一区域和具有第二掺杂浓度的第二区域。 第一掺杂浓度大于第二掺杂浓度。 翅片型半导体器件还包括氧化物层。 在鳍式半导体器件的源极和漏极形成之前，氧化物层的掺杂浓度小于第一掺杂浓度。

公开(公告)号：US20140252543A1

公开(公告)日：2014-09-11

申请号：US13784895

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/88 ,  H01L28/92 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.

Abstract translation: 特定的金属氧化物金属（MOM）电容器器件包括耦合到衬底的导电栅极材料。 MOM电容器装置还包括耦合到导电栅极材料的第一金属结构。 MOM电容器装置还包括耦合到衬底并且靠近第一金属结构的第二金属结构。

公开(公告)号：US12224347B2

公开(公告)日：2025-02-11

申请号：US17180219

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Haining Yang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：US12108610B2

公开(公告)日：2024-10-01

申请号：US17313834

申请日：2021-05-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/20 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

公开(公告)号：US11710789B2

公开(公告)日：2023-07-25

申请号：US17369532

申请日：2021-07-07

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Junjing Bao

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L27/092 ,  H01L29/24 ,  H01L29/517 ,  H01L29/66969

Abstract: Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

公开(公告)号：US20230061693A1

公开(公告)日：2023-03-02

申请号：US17410690

申请日：2021-08-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Bin Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers are disclosed. The via layer conductive structures in a signal path in an interconnect structure are disposed in respective via layers adjacent to metal lines in metal layers. The via layer conductive structures increase the conductive cross-sections of signal paths between devices in an integrated circuit (IC) or to/from an external contact. The via layer conductive structures provide one or both of supplementing the height dimensions of metal lines and electrically coupling metal lines in the same or different metal layers to increase the conductive cross-section of a signal path. The increased conductive cross-section reduces current-resistance (IR) drop of signals and increases signal speed. As metal track pitches are reduced in size, signal path resistance increases. The via layer conductive structures are provided to reduce or avoid an even greater increase in resistance in the signal paths.

公开(公告)号：US20210384227A1

公开(公告)日：2021-12-09

申请号：US16895835

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Bin Yang ,  Xia Li

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L21/84 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762

Abstract: A gate-all-around (GAA) transistor has an insulator on a substrate. The GAA transistor also may have different crystalline structures for P-type work material and N-type work material. The GAA transistor includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate section and a substrate, an insulator is added on the substrate. Further improvements are made in performance of a circuit having both P-type work material and N-type work material by providing different crystalline lattice structures for the work material.

公开(公告)号：US20200328253A1

公开(公告)日：2020-10-15

申请号：US16382904

申请日：2019-04-12

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Guoqing Chen

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  G11C13/00 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51 ,  H01L21/265

Abstract: A metal-insulator-semiconductor (MIS) resistive random access memory (RRAM) (MIS RRAM) device and MIS RRAM bit cell circuit are disclosed. A RRAM bit cell includes a RRAM device that can store a memory state and an access transistor to control access to the RRAM device. The RRAM device stores data as an electrical resistance formed in an oxide layer by applying a voltage differential between the top and bottom electrodes through the access transistor to generate an electric field in the oxide layer. This structure is similar to a metal gate formed over a channel region of a transistor. Forming the bottom electrode of the MIS RRAM device in a semiconductor structure may allow the dimensions of the electrodes of the MIS RRAM device to be scaled down to the dimensions of a transistor gate, because the MIS RRAM device structure can be fabricated with the transistor in a compatible process.

公开(公告)号：US10566413B2

公开(公告)日：2020-02-18

申请号：US15724147

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang

IPC: H01L49/02 ,  H01L21/321 ,  H01L21/768 ,  H01L27/11502 ,  H01L27/108 ,  H01L29/66 ,  H01L23/522 ,  H01L29/94 ,  H01L27/08

Abstract: A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material may include a positive capacitance material. The capacitor may further include a second insulating material disposed over the first insulating material and between the first insulating material and the second conductive layer. The second insulating material may include a negative capacitance ferroelectric material.