知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

71 records (took 0.063 seconds)

    Reference layer for perpendicular magnetic anisotropy magnetic tunnel junction
    31.
    发明授权
    Reference layer for perpendicular magnetic anisotropy magnetic tunnel junction 有权
    垂直磁各向异性磁隧道结的参考层

    公开(公告)号：US09583696B2

    公开(公告)日：2017-02-28

    申请号：US14460731

    申请日：2014-08-15

    Applicant: QUALCOMM Incorporated

    Inventor： Matthias Georg Gottwald ,  Chando Park ,  Xiaochun Zhu ,  Kangho Lee ,  Seung Hyuk Kang

    IPC: G11C11/16 ,  H01L43/08

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673

    Abstract: An apparatus includes a perpendicular magnetic anisotropy magnetic tunnel junction (pMTJ) device. The pMTJ device includes a storage layer and a reference layer. The reference layer includes a portion configured to produce a ferrimagnetic effect. The portion includes a first layer, a second layer, and a third layer. The second layer is configured to antiferromagnetically (AF) couple the first layer and the third layer during operation of the pMTJ device.

    Abstract translation: 一种装置包括垂直磁各向异性磁隧道结（pMTJ）装置。 pMTJ设备包括存储层和参考层。 参考层包括被配置为产生亚铁磁效应的部分。 该部分包括第一层，第二层和第三层。 第二层被配置为在pMTJ器件的操作期间反铁磁（AF）耦合第一层和第三层。

    Adjusting resistive memory write driver strength based on write error rate (WER) to improve WER yield, and related methods and systems
    32.
    发明授权
    Adjusting resistive memory write driver strength based on write error rate (WER) to improve WER yield, and related methods and systems 有权
    基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度，以提高WER产量，以及相关方法和系统

    公开(公告)号：US09455014B1

    公开(公告)日：2016-09-27

    申请号：US14818809

    申请日：2015-08-05

    Applicant: QUALCOMM Incorporated

    Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

    IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C29/44

    CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

    Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

    Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

    Magnesium oxide capping with a shorted path for perpendicular magnetic tunnel junction devices and method for fabrication
    33.
    发明授权
    Magnesium oxide capping with a shorted path for perpendicular magnetic tunnel junction devices and method for fabrication 有权
    用于垂直磁隧道结装置的短路径的氧化镁封盖及其制造方法

    公开(公告)号：US09444035B2

    公开(公告)日：2016-09-13

    申请号：US14483104

    申请日：2014-09-10

    Applicant: QUALCOMM Incorporated

    Inventor： Chando Park ,  Kangho Lee ,  Jimmy Kan ,  Matthias Georg Gottwald ,  Xiaochun Zhu ,  Seung Hyuk Kang

    IPC: H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

    CPC classification number: H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic tunnel junction (MTJ) device includes a pinned layer, a tunnel barrier layer on the pinned layer, and a free layer on the tunnel barrier layer. The MTJ device also includes a perpendicular magnetic anisotropic (PMA) enhancement layer on the free layer, a capping layer on the PMA enhancement layer, and a conductive path electrically shorting the capping layer, the PMA enhancement layer and the free layer. A method of fabricating a perpendicular magnetic tunnel junction (pMTJ) device includes forming a capping layer, a perpendicular magnetic anisotropic (PMA) enhancement layer and a free layer. The method also includes forming a conductive layer to short the capping layer, the PMA enhancement layer and the free layer.

    Abstract translation: 磁性隧道结（MTJ）装置包括钉扎层，钉扎层上的隧道势垒层和隧道势垒层上的自由层。 MTJ装置还包括在自由层上的垂直磁各向异性（PMA）增强层，PMA增强层上的覆盖层以及电封闭封盖层，PMA增强层和自由层的导电路径。 制造垂直磁性隧道结（pMTJ）器件的方法包括形成覆盖层，垂直磁性各向异性（PMA）增强层和自由层。 该方法还包括形成导电层以缩短封盖层，PMA增强层和自由层。

    Physically unclonable function based on the random logical state of magnetoresistive random-access memory
    34.
    发明授权
    Physically unclonable function based on the random logical state of magnetoresistive random-access memory 有权
    基于磁阻随机存取存储器的随机逻辑状态的物理不可克隆功能

    公开(公告)号：US09214214B2

    公开(公告)日：2015-12-15

    申请号：US14072634

    申请日：2013-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

    IPC: G11C11/16 ,  H04L9/30 ,  H04L9/32

    CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

    Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.

    Abstract translation: 一个特征涉及实现物理不可克隆功能（PUF）的方法。 该方法包括将磁阻随机存取存储器（MRAM）阵列阵列暴露于正交外部磁场。 MRAM单元各自被配置为表示第一逻辑状态和第二逻辑状态之一，并且正交外部磁场定向为与MRAM单元的自由层的容易轴正交的方向，以将MRAM单元置于 不是第一逻辑状态或第二逻辑状态的中性逻辑状态。 该方法还包括去除正交的外部磁场，将阵列的每个MRAM单元随机地置于第一逻辑状态或第二逻辑状态中。

    Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM)
    35.
    发明授权
    Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM) 有权
    降低自旋转矩磁阻随机存取存储器（STT-MRAM）中的源负载效应

    公开(公告)号：US09105340B2

    公开(公告)日：2015-08-11

    申请号：US14027503

    申请日：2013-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Kangho Lee ,  Seung H. Kang ,  Xiachun Zhu

    IPC: G11C11/00 ,  G11C11/16 ,  H01L43/02

    CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

    Abstract: A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

    Abstract translation: 存储单元包括磁隧道结（MTJ）结构，其包括耦合到位线和固定层的自由层。 自由层的磁矩基本上平行于处于第一状态的被钉扎层的磁矩，并且在第二状态下基本上与销钉层的磁矩反平行。 固定层具有物理尺寸以产生对应于MTJ结构的第一开关电流的偏移磁场，以便当第一电压从位线施加到耦合到第一状态的源极线时，能够在第一状态和第二状态之间切换 存取晶体管和第二开关电流，以便当第一电压从源极线施加到位线时，能够在第二状态和第一状态之间切换。

    FABRICATION OF A MAGNETIC TUNNEL JUNCTION DEVICE
    36.
    发明申请
    FABRICATION OF A MAGNETIC TUNNEL JUNCTION DEVICE 有权
    一种磁性隧道连接装置的制造

    公开(公告)号：US20140038312A1

    公开(公告)日：2014-02-06

    申请号：US14048918

    申请日：2013-10-08

    Applicant: QUALCOMM Incorporated

    Inventor： Kangho Lee ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

    IPC: H01L43/02

    CPC classification number: H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  G06F17/5068 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/309 ,  H01F41/32 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

    Abstract translation: 公开了一种磁性隧道接合装置及其制造方法。 在特定实施例中，非暂时计算机可读介质包括处理器可执行指令。 当处理器执行时，指令使处理器开始在磁隧道结结构的自由层上沉积封盖材料以形成覆盖层。 所述指令在由所述处理器执行时使所述处理器启动所述封盖材料的第一层的氧化以形成氧化材料的第一氧化层。

Patent Agency Ranking