公开(公告)号：US10079097B2

公开(公告)日：2018-09-18

申请号：US14736219

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01G4/228 ,  H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G2/06 ,  H01G4/232

CPC classification number: H01G4/228 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

公开(公告)号：US09613942B2

公开(公告)日：2017-04-04

申请号：US14733201

申请日：2015-06-08

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/065 ,  H01L23/50 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06548 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

公开(公告)号：US09502490B2

公开(公告)日：2016-11-22

申请号：US14283980

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L49/02 ,  H01L23/498 ,  H05K1/18 ,  H05K3/46 ,  H01L23/50

CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

公开(公告)号：US20160247761A1

公开(公告)日：2016-08-25

申请号：US14631391

申请日：2015-02-25

Applicant: QUALCOMM INCORPORATED

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5227 ,  H01F27/2847 ,  H01F27/292 ,  H01F41/063 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

Abstract translation: 集成器件封装包括封装衬底，耦合到封装衬底的管芯，封装管芯的封装层以及配置成作为电感器工作的至少一片导电材料。 导电材料片材至少部分地被封装层封装。 导电材料片被配置为作为螺线管电感器工作。 导电材料片包括第一片部分，第二片部分，其耦合到第一片部分，第一片部分和第二片部分形成电感器的第一绕组，第一端部分耦合到第一片 部分，以及耦合到第二片部分的第二端子部分。 第一片部分形成在片材的第一层上。 第二片部分形成在片材的第二层上。

公开(公告)号：US20160225748A1

公开(公告)日：2016-08-04

申请号：US14609079

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Kyu-Pyung Hwang

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A method for forming a package-on-package (POP) structure is disclosed. The method includes placing a post on a first integrated circuit (IC) package such that a solder coating disposed on a first surface of the post is between the post and a second surface of the first IC package. The post is placed at a distance from a die along a particular axis of the die. The particular axis is substantially parallel to the second surface. The first IC package includes the die. The method also includes forming a conductive path between a second IC package and the first IC package via the post and a solder bump. The solder bump is disposed between the post and the second IC package.

Abstract translation: 公开了一种用于形成封装封装（POP）结构的方法。 该方法包括将柱放置在第一集成电路（IC）封装上，使得布置在柱的第一表面上的焊料涂层位于第一IC封装的柱和第二表面之间。 柱沿模具的特定轴线放置在离模具一定距离处。 特定轴线基本上平行于第二表面。 第一个IC封装包括裸片。 该方法还包括在第二IC封装和第一IC封装之间经由柱和焊料凸块形成导电路径。 焊料凸块设置在柱和第二IC封装之间。

公开(公告)号：US20160141234A1

公开(公告)日：2016-05-19

申请号：US14543560

申请日：2014-11-17

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/498

CPC classification number: H01L23/5385 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2203/061 ,  H01L2924/00

Abstract: An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

Abstract translation: 集成器件封装包括基部，再分配部分，第一管芯和第二管芯。 基部包括可照像图像层，至少部分地嵌入在可照光成像层中的桥以及可照片成像层中的一组通孔。 桥包括包括第一密度的第一组互连。 该组通孔包括第二密度。 再分配部分耦合到基部。 再分配部分包括耦合到第一组互连的至少一个电介质层，第二组互连以及耦合到该组通孔的第三组互连。 第一管芯耦合到再分配部分。 第二管芯耦合到再分配部分，其中第一管芯和第二管芯通过包括桥的电路相互连接。

公开(公告)号：US20150228556A1

公开(公告)日：2015-08-13

申请号：US14274517

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/50

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和焊盘的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：US12100645B2

公开(公告)日：2024-09-24

申请号：US17482718

申请日：2021-09-23

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/49822

Abstract: Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.

公开(公告)号：US11955409B2

公开(公告)日：2024-04-09

申请号：US17148257

申请日：2021-01-13

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Joan Rey Villarba Buot ,  Hong Bok We

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/12 ,  H01L23/66

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/12 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6638

Abstract: A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

公开(公告)号：US11948877B2

公开(公告)日：2024-04-02

申请号：US17211164

申请日：2021-03-24

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Brigham Navaja

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/3135 ,  H01L23/49822 ,  H01L25/105 ,  H01L21/4853 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2225/1035

Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.