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    Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask
    32.
    发明授权
    Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask 有权

    公开(公告)号：US09704746B1

    公开(公告)日：2017-07-11

    申请号：US15235892

    申请日：2016-08-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jiehui Shu ,  Jinping Liu ,  Archana Subramaniyan

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02

    CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31144

    Abstract: A method of forming a metallization layer by ASAP is provided. Embodiments include forming an ULK layer; forming a SAC SiN layer over the ULK layer; forming mandrels directly on the SAC SiN layer; cutting the mandrels; selectively etching the SAC SiN layer across the cut mandrels, forming first trenches; filling the first trenches with a metal oxide; forming a conformal metal oxide layer over the cut mandrels, the metal oxide, and the SAC SiN layer; removing horizontal portions of the conformal metal oxide layer over the cut mandrels and the SAC SiN layer; removing the cut mandrels; removing exposed portions of the SAC SiN layer and etching the underlying ULK layer, forming second trenches; and stripping a remainder of the metal oxide, conformal metal oxide layer, and SAC SiN layer.

    Method for eliminating interlayer dielectric dishing and controlling gate height uniformity
    33.
    发明授权
    Method for eliminating interlayer dielectric dishing and controlling gate height uniformity 有权
    消除层间电介质凹陷和控制栅极高度均匀性的方法

    公开(公告)号：US09589807B1

    公开(公告)日：2017-03-07

    申请号：US15164146

    申请日：2016-05-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Yuanfang Lu

    IPC: H01L21/283 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66

    CPC classification number: H01L21/283 ,  H01L21/32137 ,  H01L21/76224 ,  H01L21/76837 ,  H01L21/7684 ,  H01L29/66545 ,  H01L29/6656

    Abstract: A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.

    Abstract translation: 提供消除层间电介质（ILD）凹陷并控制栅极高度均匀性的方法。 实施例包括在衬底上形成多个多晶硅栅极，每个栅极具有形成在多晶硅栅极侧面上的隔离物和形成在上表面上的氮化物盖; 在相邻的多晶硅栅极之间形成间隙填充材料; 在相邻的多晶硅栅极之间的间隙填充材料上形成氧化物; 去除氮化物盖; 去除相邻多晶硅栅极之间的氧化物的一部分，形成凹陷; 以及在相邻的多晶硅栅极之间的凹槽中形成ILD覆盖层。

    10 nm alternative N/P doped fin for SSRW scheme
    35.
    发明授权
    10 nm alternative N/P doped fin for SSRW scheme 有权
    用于SSRW方案的10nm替代N / P掺杂散热片

    公开(公告)号：US09455204B1

    公开(公告)日：2016-09-27

    申请号：US14727143

    申请日：2015-06-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Huy M. Cao ,  Jinping Liu ,  Guillaume Bouche ,  Huang Liu

    IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823892 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

    Abstract: A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments include forming a plurality of p-type and n-type fins on a substrate, the plurality of p-type and n-type fins formed with an ISSG or pad oxide layer; performing an n-well implant into the substrate through the ISSG or pad oxide layer; performing a first SRPD on the ISSG or pad oxide layer of the plurality of p-type fins; performing a p-well implant into the substrate through the ISSG or pad oxide layer; performing a second SRPD on the ISSG or pad oxide layer of the plurality of n-type fins; and driving the n-well and p-well implants and the SRPD dopants into a portion of the plurality of p-type and n-type fins.

    Abstract translation: 在SSRW层的PMOS和NMOS鳍片中引入N / P掺杂剂而不需要复杂的处理并提供所得到的器件的方法。 实施例包括在基板上形成多个p型和n型翅片，多个p型和n型翅片形成有ISSG或衬垫氧化物层; 通过ISSG或衬垫氧化物层将n阱注入到衬底中; 在多个p型翅片的ISSG或衬垫氧化物层上执行第一SRPD; 通过ISSG或垫氧化物层进行p阱注入到衬底中; 在所述多个n型鳍片的ISSG或衬垫氧化物层上执行第二SRPD; 并且将n阱和p阱注入和SRPD掺杂剂驱动到多个p型和n型鳍中的一部分中。

    Semiconductor structure with increased space and volume between shaped epitaxial structures
    38.
    发明授权
    Semiconductor structure with increased space and volume between shaped epitaxial structures 有权
    成形外延结构之间的空间和体积增加的半导体结构

    公开(公告)号：US09165767B2

    公开(公告)日：2015-10-20

    申请号：US14071170

    申请日：2013-11-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Bharat Krishnan ,  Jody A. Fronheiser ,  Jinping Liu ,  Bongki Lee

    IPC: H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

    CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

    Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延生长在增加的（100）区域。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长附加外延的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并，同时 也增加了他们的体积。

    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS
    39.
    发明申请
    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS 有权
    用于CMOS应用和结果产品的晶体管器件的门结构的方法

    公开(公告)号：US20150061027A1

    公开(公告)日：2015-03-05

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L27/092 ,  H01L21/28

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

    METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARRIER LOWERING AND ON RESISTANCE
    40.
    发明申请
    METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARRIER LOWERING AND ON RESISTANCE 审中-公开
    具有减少排水诱导障碍物下降和抗电阻的晶体管的方法和结构

    公开(公告)号：US20140159052A1

    公开(公告)日：2014-06-12

    申请号：US13710639

    申请日：2012-12-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jinping Liu ,  Yi Qi ,  Xiaodong Yang

    IPC: H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    Abstract: Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and RON. A sigma cavity is formed in a semiconductor substrate adjacent to a transistor. The sigma cavity is filled with an epitaxially grown semiconductor material that also serves as a stress-inducing region for the purposes of increasing carrier mobility. The epitaxially grown semiconductor material is doped with a reverse doping profile. A lightly doped region lines the interior of the sigma cavity, followed by an undoped region, followed by a heavily doped region. The shape of the lightly doped region is such that it is thicker adjacent to the channel, which reduces RON, and thinner below the channel, which reduces DIBL.

    Abstract translation: 本发明的实施例提供了具有减少的DIBL和RON的晶体管的改进的方法和结构。 在与晶体管相邻的半导体衬底中形成Σ腔。 填充有外延生长的半导体材料，其也用作应力诱导区域，以增加载流子迁移率。 外延生长的半导体材料掺杂有反向掺杂分布。 轻掺杂区域将西格玛腔体的内部引导，随后是未掺杂的区域，随后是重掺杂区域。 轻掺杂区域的形状使其在沟道附近较厚，这降低了RON，并且在沟道以下更薄，这降低了DIBL。

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