公开(公告)号：US11264463B2

公开(公告)日：2022-03-01

申请号：US16883492

申请日：2020-05-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/161 ,  H01L29/16 ,  H01L23/482 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

公开(公告)号：US10453750B2

公开(公告)日：2019-10-22

申请号：US15629884

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej J. Pawlak ,  Guillaume Bouche ,  Ajey P. Jacob

IPC: H01L25/07 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775

Abstract: Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

公开(公告)号：US20190229196A1

公开(公告)日：2019-07-25

申请号：US16253321

申请日：2019-01-22

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Julien Ryckaert ,  Juergen Boemmels ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/41791 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

公开(公告)号：US10249728B2

公开(公告)日：2019-04-02

申请号：US15955989

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Andre Labonte ,  Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Guillaume Bouche

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L29/40 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/8234

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US10242867B2

公开(公告)日：2019-03-26

申请号：US15598393

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Vimal Kamineni

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49

Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.

公开(公告)号：US10199271B1

公开(公告)日：2019-02-05

申请号：US15693651

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Guillaume Bouche ,  Laertis Economikos ,  Lei Sun ,  Guoxiang Ning ,  Xunyuan Zhang

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L23/535 ,  H01L21/285 ,  H01L23/532 ,  H01L23/528

Abstract: A structure and method for forming a self-aligned metal wire on a contact structure. The method for forming the self-aligned metal wire and contact structure may include, among other things, forming an initial contact structure above a substrate; forming a patterned mask on the initial contact structure, the mask including an opening; using the patterned mask to form an opening through the initial contact structure; forming a dielectric layer in the openings; removing the patterned mask to expose a remaining portion of the initial contact structure; and forming the metal wire on the remaining portion of the initial contact structure. The contact structure may include a vertical cross-sectional geometry including one of a trapezoid wherein a bottommost surface of the first contact structure is wider than an uppermost surface of the first contact structure, and a parallelogram. The metal wire may completely contact an uppermost surface of the contact structure.

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US10083858B2

公开(公告)日：2018-09-25

申请号：US15800551

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas Vincent Licausi ,  Guillaume Bouche

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286

Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.

公开(公告)号：US10014390B1

公开(公告)日：2018-07-03

申请号：US15729105

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Julien Frougier ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308 ,  H01L29/423

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/3086 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696 ,  H01L2029/42388

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a first nanosheet channel layer, a second nanosheet channel layer, and first, second, and third sacrificial layers that are vertically arranged between the first and second nanosheet channel layers. The first, second, and third sacrificial layers are laterally recessed relative to the first and second nanosheet channel layers to form a cavity indented into a sidewall of the first body feature. The second sacrificial layer is laterally recessed to a lesser extent than the first sacrificial layer or the third sacrificial layer such that an end of the second sacrificial layer projects into the cavity between the first and third sacrificial layers. A dielectric spacer is formed in the first and second portions of cavity between the first and second nanosheet channel layers.

公开(公告)号：US20180005893A1

公开(公告)日：2018-01-04

申请号：US15703601

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Huang Liu ,  Guillaume Bouche ,  Songkram Srivathanakul

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823821 ,  H01L29/66795

Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate. A patterned mask layer is formed above the process layer. The patterned mask layer includes first openings exposing portions of the process layer. A carbon-containing silicon dioxide layer is formed above the patterned mask layer and in the first openings. The carbon-containing silicon dioxide layer is planarized to remove portions extending outside the first openings and generate a plurality of mask elements from remaining portions of the carbon-containing silicon dioxide layer. The patterned mask layer is removed. The process layer is etched using the mask elements as an etch mask.