公开(公告)号：US10290633B2

公开(公告)日：2019-05-14

申请号：US15997154

申请日：2018-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/00 ,  H01L27/06 ,  H01L23/525 ,  H01L49/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L23/528

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

公开(公告)号：US20190123199A1

公开(公告)日：2019-04-25

申请号：US16230340

申请日：2018-12-21

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Oleg Gluschenkov ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7842 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.

公开(公告)号：US10269644B2

公开(公告)日：2019-04-23

申请号：US15680697

申请日：2017-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/8234

Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.

公开(公告)号：US10224420B2

公开(公告)日：2019-03-05

申请号：US15656326

申请日：2017-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L29/417

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

公开(公告)号：US10177154B2

公开(公告)日：2019-01-08

申请号：US15691182

申请日：2017-08-30

Applicant: International Business Machines Corporation

Inventor： Michael V. Aquilino ,  Veeraraghavan S. Basker ,  Kangguo Cheng ,  Gregory Costrini ,  Ali Khakifirooz ,  Byeong Y. Kim ,  William L. Nicoll ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Hanfei Wang ,  Xinhui Wang

IPC: H01L29/94 ,  H01L27/108 ,  H01L27/12 ,  H01L27/08

Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

公开(公告)号：US10170594B2

公开(公告)日：2019-01-01

申请号：US15715593

申请日：2017-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/417 ,  H01L21/265 ,  H01L21/225 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

公开(公告)号：US10157912B2

公开(公告)日：2018-12-18

申请号：US15665897

申请日：2017-08-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L27/11 ,  H01L27/06 ,  H01L23/525 ,  H01L49/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L23/528

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

公开(公告)号：US10096484B2

公开(公告)日：2018-10-09

申请号：US15483125

申请日：2017-04-10

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/308 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L23/535 ,  H01L21/306 ,  H01L21/768

Abstract: A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.

公开(公告)号：US20180277676A1

公开(公告)日：2018-09-27

申请号：US15992733

申请日：2018-05-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66553 ,  H01L29/66666

Abstract: A transistor includes a vertical channel fin on a bottom source/drain region. The vertical channel fin includes a base portion and an upper portion. The base portion has a width greater than a width of the upper portion and a top surface height greater than a top surface height of the bottom source/drain region. A gate stack formed on sidewalls of the vertical channel fin. Spacers are formed above the gate stack, one above each sidewall of the vertical channel fin. A top source/drain region is formed between the spacers.

公开(公告)号：US10083972B2

公开(公告)日：2018-09-25

申请号：US15366015

申请日：2016-12-01

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/11 ,  H01L29/51 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L27/1116 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/5226 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/785

Abstract: The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the dielectric layer exposing a source drain region of a logic device, forming a third opening in the dielectric layer exposing a gate of the SRAM device and forming a fourth opening in the dielectric layer exposing a gate of the logic device, forming a first sidewall spacer in the third opening and forming a second sidewall spacer in the fourth opening, recessing a portion of the first sidewall spacer without recessing the second sidewall spacer, forming a strapped contact in the first and third openings, the strapped contact creates an electrical connection between the source drain region of the SRAM device and the gate of the SRAM device, the electrical connection is directly above a remaining portion of the first sidewall spacer.