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    Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages
    31.
    发明申请
    Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages 审中-公开
    具有多个阈值电压的本征信道平面场效应晶体管

    公开(公告)号：US20150021698A1

    公开(公告)日：2015-01-22

    申请号：US13945086

    申请日：2013-07-18

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  Ramachandra Divakaruni ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Arvind Kumar ,  Unoh Kwon ,  Barry P. Linder ,  Vijay Narayanan

    IPC: H01L27/088 ,  H01L21/28

    CPC classification number: H01L27/0886 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/7833

    Abstract: Intrinsic channels one or more intrinsic semiconductor materials are provided in a semiconductor substrate. A high dielectric constant (high-k) gate dielectric layer is formed on the intrinsic channels. A patterned diffusion barrier metallic nitride layer is formed. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one work function material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks.

    Abstract translation: 本征通道在半导体衬底中提供一个或多个本征半导体材料。 在内部通道上形成高介电常数（高k）栅介质层。 形成图案化扩散阻挡金属氮化物层。 在高k栅极电介质层和扩散阻挡金属氮化物层的物理暴露部分上形成阈值电压调整氧化物层。 执行退火以将阈值电压调节氧化物层的材料驱动到本征通道和高k栅极电介质层之间的界面，从而形成阈值电压调节氧化物部分。 形成至少一个功函数材料层，并且利用高k栅介质层和阈值电压调整氧化物部分图案化以形成多种类型的栅堆叠。

    COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE HAVING GATE STRUCTURES CONNECTED BY A METAL GATE CONDUCTOR
    32.
    发明申请
    COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE HAVING GATE STRUCTURES CONNECTED BY A METAL GATE CONDUCTOR 有权
    具有由金属栅导体连接的门结构的补充金属氧化物半导体（CMOS）器件

    公开(公告)号：US20140349451A1

    公开(公告)日：2014-11-27

    申请号：US14292312

    申请日：2014-05-30

    Applicant: International Business Machines Corporation

    Inventor： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

    IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/306 ,  H01L21/28 ,  H01L29/49

    CPC classification number: H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

    Abstract translation: 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

    STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY
    34.
    发明申请
    STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY 有权
    高k金属门技术的镀层结构与方法

    公开(公告)号：US20140170844A1

    公开(公告)日：2014-06-19

    申请号：US14167532

    申请日：2014-01-29

    Applicant: International Business Machines Corporation

    Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

    IPC: H01L21/28

    CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

    Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.

    Abstract translation: 提供包括缩放的n沟道场效应晶体管（nFET）和缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分来提供这种结构。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以等离子体氮化。 等离子体氮化nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质。

    REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
    35.
    发明申请
    REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT 有权
    更换提供工作功能和门漏电流的独立控制的金属门结构

    公开(公告)号：US20130193522A1

    公开(公告)日：2013-08-01

    申请号：US13789018

    申请日：2013-03-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

    IPC: H01L27/092

    CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

    Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

    Abstract translation: 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

    REPLACEMENT GATE HAVING WORK FUNCTION AT VALENCE BAND EDGE
    36.
    发明申请
    REPLACEMENT GATE HAVING WORK FUNCTION AT VALENCE BAND EDGE 有权
    更换门槛在瓦楞带边缘的工作功能

    公开(公告)号：US20130161764A1

    公开(公告)日：2013-06-27

    申请号：US13770552

    申请日：2013-02-19

    Applicant: International Business Machines Corporation

    Inventor： Keith Kwong Hon Wong ,  Michael P. Chudzik ,  Unoh Kwon

    IPC: H01L29/51

    CPC classification number: H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    Abstract: Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

    Abstract translation: 提供了替代栅极堆叠，这增加了p型场效应晶体管（PFET）的栅电极的功函数。 在一个实施例中，功函数金属堆叠包括位于下部氮化钛层和上部氮化钛层之间的氧化钛 - 氮化物层。 下部氮化钛层，钛氧化物 - 氮化物层和上部氮化钛层的堆叠产生显着增加功函数金属叠层功函数的意想不到的结果。 在另一个实施例中，功函数金属堆叠包括在不高于420℃的温度下沉积的铝层。在不高于420℃的温度下沉积的铝层产生增加工件功函数的意想不到的结果 功能金属堆叠显着。

    Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET
    37.
    发明申请
    Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET 有权
    用于高K金属栅P型MOSFET的低阈值电压和反转氧化物厚度缩放

    公开(公告)号：US20130034940A1

    公开(公告)日：2013-02-07

    申请号：US13630235

    申请日：2012-09-28

    Applicant: International Business Machines Corporation

    Inventor： Takashi ANDO ,  Changhwan Choi ,  Martin M. Frank ,  Unoh Kwon ,  Vijay Narayanan

    IPC: H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/517

    Abstract: A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.

    Abstract translation: 一种形成半导体结构的方法。 半导体结构具有半导体衬底以及设置在衬底上的nFET和pFET。 pFET具有形成在半导体衬底的表面上或其表面上的半导体SiGe沟道区，以及覆盖沟道区的氧化物层和覆盖氧化物层的高k电介质层的栅极电介质。 栅电极覆盖在栅极电介质上，并且具有邻接高k层的下金属层，邻接下金属层的清除金属层和与清除金属层邻接的上金属层。 金属层清除了衬底（nFET）中的氧和与氧化物层的SiGe（pFET）界面，导致pFET的Tinv和Vt有效降低，同时缩放Tinv并维持nFET的Vt，导致Vt pFET变得更接近具有缩放Tinv值的类似构造的nFET的Vt。

    Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages
    38.
    发明授权
    Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages 有权

    公开(公告)号：US11031301B2

    公开(公告)日：2021-06-08

    申请号：US16691803

    申请日：2019-11-22

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Unoh Kwon ,  Vijay Narayanan

    IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28

    Abstract: Embodiments of the invention include a wafer having gate stacks over channel fins. The wafer includes a first channel fin in an n-type region of a substrate, a second channel fin in a p-type region of the substrate, and a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is over the gate dielectric, the first channel fin in the n-type region, and the second channel fin in the p-type region. The work function metal stack over the gate dielectric and the first channel fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes a shared layer of work function metal shared with the second work function metal stack.

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