公开(公告)号：US20180300903A1

公开(公告)日：2018-10-18

申请号：US15489068

申请日：2017-04-17

申请人： Intel Corporation

发明人： John G. Gierach ,  Hugues Labbe ,  Tomer Bar-On ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Philip R. Laws ,  Devan Burke ,  Abhishek R. Appu ,  Peter L. Doyle ,  Elmoustapha Ould-Ahmed-Vall ,  Travis T. Schluessler ,  Altug Koker

IPC分类号： G06T9/00 ,  G06T1/20 ,  G06T7/194 ,  G09G3/00 ,  G06T15/20 ,  G06T15/50 ,  G06T1/60

摘要： Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.

公开(公告)号：US20180300098A1

公开(公告)日：2018-10-18

申请号：US15489096

申请日：2017-04-17

申请人： Intel Corporation

发明人： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC分类号： G06F3/14 ,  H04L29/06

摘要： An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20180285109A1

公开(公告)日：2018-10-04

申请号：US15477012

申请日：2017-04-01

申请人： Intel Corporation

发明人： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC分类号： G06F9/30 ,  G06T1/60 ,  G06F9/50 ,  G06F12/0802 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

摘要： Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US09894752B2

公开(公告)日：2018-02-13

申请号：US14678714

申请日：2015-04-03

申请人： Intel Corporation

发明人： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

IPC分类号： H01F27/28 ,  H01F41/04 ,  H05K1/02 ,  H05K1/16 ,  H01F17/00 ,  H05K1/11

CPC分类号： H05K1/0237 ,  H01F17/0013 ,  H01F2017/002 ,  H05K1/0233 ,  H05K1/116 ,  H05K1/165

摘要： Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

公开(公告)号：US20170310404A1

公开(公告)日：2017-10-26

申请号：US15421192

申请日：2017-01-31

申请人： Intel Corporation

发明人： Kai Xiao

IPC分类号： H04B17/15 ,  H04B3/48 ,  H04B17/10

CPC分类号： H04B3/48 ,  G01R35/005 ,  H04B3/46 ,  H04B17/102 ,  H04B17/103 ,  H04B17/104 ,  H04B17/15

摘要： Technologies for determining the parameters of a transmission line such as a printed circuit board trace and a cable are disclosed. By measuring a reflection coefficient and a transmission coefficient of two different electrical structures with the same type of fixture on each end and transmission lines of different lengths, the attenuation coefficient of the transmission lines can be determined. The attenuation coefficient can indicate whether or not the performance of the transmission line is acceptable or may be used to calibrate a measuring device for subsequent measurements.

公开(公告)号：US09338882B2

公开(公告)日：2016-05-10

申请号：US14278330

申请日：2014-05-15

申请人： Intel Corporation

发明人： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang

IPC分类号： H05K1/02 ,  H01P3/02 ,  H01P3/08 ,  H01P11/00 ,  B33Y10/00 ,  B33Y80/00

CPC分类号： H05K1/0245 ,  B33Y10/00 ,  B33Y80/00 ,  H01P3/02 ,  H01P3/08 ,  H01P11/003 ,  H05K2201/09281 ,  Y10T29/49156

摘要： A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.

摘要翻译： 这里描述了宽边耦合差分设计。 该设计可以包括差分对。 差分对的每个迹线包括宽部分和窄部分。 差分对的第一迹线的宽部分将与差分对的第二迹线的窄部分对准。 此外，差分对的第二迹线的宽部分将与差分对的第一迹线的窄部分对齐，使得差分对的迹线的宽和窄部分交错。

公开(公告)号：US09131603B2

公开(公告)日：2015-09-08

申请号：US13844761

申请日：2013-03-15

申请人： INTEL CORPORATION

发明人： Kai Xiao ,  Jimmy Hsu ,  Yuan-Liang Li ,  Richard K. Kunze

IPC分类号： H05K1/02 ,  H01P3/08 ,  H01P11/00

CPC分类号： H05K1/0228 ,  H01P3/08 ,  H01P11/00 ,  H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09709 ,  Y10T29/49155

摘要： A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.

摘要翻译： 这里描述了信号线设计。 电路板可以包括第一信号线和第二信号线。 第一信号线包括在电路板的一部分的第一深度处的一对信号线，其中中心线在该对信号线之间纵向延伸。 第二信号线设置在电路板的第二深度处。 第二信号线包括第一段，该第一段在与中心线的第一位移处平行于第一信号线延伸。 第二信号线包括与中心线的另一侧平行于第一信号线的第二段，距中心线的第二位移距离。

公开(公告)号：US11632130B2

公开(公告)日：2023-04-18

申请号：US17681364

申请日：2022-02-25

申请人： Intel Corporation

发明人： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC分类号： H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

摘要： An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US11461959B2

公开(公告)日：2022-10-04

申请号：US16865587

申请日：2020-05-04

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Balaji Vembu ,  Michael Apodaca ,  Slawomir Grajewski ,  Gabor Liktor ,  David M. Cimini ,  Andrew T. Lauritzen ,  Travis T. Schluessler ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Kai Xiao ,  Ankur N. Shah ,  Altug Koker

IPC分类号： G06T15/40 ,  G06T1/20 ,  G06T15/30 ,  G06T15/00 ,  G06T11/40 ,  G06T17/20

摘要： The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

公开(公告)号：US20220021139A1

公开(公告)日：2022-01-20

申请号：US17483913

申请日：2021-09-24

申请人： Intel Corporation

发明人： Xiang Li ,  Shaohua Li ,  Kai Xiao ,  Mo Liu ,  Jingbo Li

IPC分类号： H01R12/57 ,  H01R12/72 ,  H01R12/73

摘要： In one embodiment, a card edge connector includes a housing including a slot to receive a first circuit board. A first plurality of pins extend from within the slot through a bottom of the housing. Each of the first plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of contacts of a second circuit board, the second end including a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot. A second plurality of pins extend from within the slot through the bottom of the housing. Each of the second plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a second plurality of contacts of the second circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction toward the centerline of the slot. Other embodiments are described and claimed.