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公开(公告)号：US20230215400A1
公开(公告)日：2023-07-06
申请号：US18179067
申请日：2023-03-06
Applicant: Intel Corporation
Inventor： Louis Feng , Altug Koker , Tomasz Janczak , Andrew T. Lauritzen , David M. Cimini , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws , Devan Burke , Elmoustapha Ould-Ahmed-Vall , Abhishek R. Appu
CPC classification number: G09G5/005 , G06T1/20 , G09G5/001 , G09G5/38 , G09G5/363 , G09G5/391 , G09G2360/06 , G09G2360/08 , G09G2360/121 , G09G2360/125
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US11120766B2
公开(公告)日：2021-09-14
申请号：US16512964
申请日：2019-07-16
Applicant: Intel Corporation
Inventor： Louis Feng , Altug Koker , Tomasz Janczak , Andrew T. Lauritzen , David M. Cimini , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws , Devan Burke , Elmoustapha Ould-Ahmed-Vall , Abhishek R. Appu
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US10970538B2
公开(公告)日：2021-04-06
申请号：US16181921
申请日：2018-11-06
Applicant: Intel Corporation
Inventor： Radhakrishnan Venkataraman , James M. Holland , Sayan Lahiri , Pattabhiraman K , Kamal Sinha , Chandrasekaran Sakthivel , Daniel Pohl , Vivek Tiwari , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , Eimoustapha Ould-Ahmed-Vall , Peter L. Doyle , Devan Burke
Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.
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公开(公告)号：US10930046B2
公开(公告)日：2021-02-23
申请号：US16269049
申请日：2019-02-06
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws
IPC: G06T15/00 , H04N13/398 , H04N13/344
Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
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公开(公告)号：US20200348897A1
公开(公告)日：2020-11-05
申请号：US16881262
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam M. Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/14 , G06F3/01 , G09G5/391 , G06F3/0484
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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Patent Agency Ranking
公开(公告)号：US10691392B2
公开(公告)日：2020-06-23
申请号：US15488758
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam M. Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/01 , G06F3/14 , G09G5/391 , G06F3/0484 , G09G5/00
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号：US10242496B2
公开(公告)日：2019-03-26
申请号：US15494696
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Peter L. Doyle , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall , Philip R. Laws , Altug Koker
Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.
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公开(公告)号：US20240404487A1
公开(公告)日：2024-12-05
申请号：US18736899
申请日：2024-06-07
Applicant: Intel Corporation
Inventor： Louis Feng , Altug Koker , Tomasz Janczak , Andrew T. Lauritzen , David M. Cimini , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws , Devan Burke , Elmoustapha Ould-Ahmed-Vall , Abhishek R. Appu
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US11605197B2
公开(公告)日：2023-03-14
申请号：US17180188
申请日：2021-02-19
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws
IPC: G06T15/00 , H04N13/398 , H04N13/344
Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
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公开(公告)号：US20210304485A1
公开(公告)日：2021-09-30
申请号：US17180188
申请日：2021-02-19
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws
IPC: G06T15/00 , H04N13/344 , H04N13/398
Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
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