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公开(公告)号：US20220245752A1
公开(公告)日：2022-08-04
申请号：US17685445
申请日：2022-03-03
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.
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公开(公告)号：US20220066726A1
公开(公告)日：2022-03-03
申请号：US17399103
申请日：2021-08-11
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam M. Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/14 , G06F3/01 , G09G5/391 , G06F3/0484
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号：US11099800B2
公开(公告)日：2021-08-24
申请号：US16881262
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam M. Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/14 , G06F3/01 , G09G5/391 , G06F3/0484 , G09G5/00
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号：US20210125581A1
公开(公告)日：2021-04-29
申请号：US17062871
申请日：2020-10-05
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, JR. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F12/0875 , G06F9/46 , G09G5/00
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US10453427B2
公开(公告)日：2019-10-22
申请号：US15477030
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan Bhairavabhatla , Arthur D. Hunter, Jr. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F9/46 , G06F12/0875 , G09G5/00 , G06F12/084 , G06F12/0811
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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Patent Agency Ranking
公开(公告)号：US20180308197A1
公开(公告)日：2018-10-25
申请号：US15493420
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , Subramaniam M. Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , James A. Valerio , Eric J. Hoekstra , Arthur D. Hunter, JR.
CPC classification number: G06T1/20 , G06F9/223 , G06F9/4496 , G06T15/04
Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
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公开(公告)号：US20180308196A1
公开(公告)日：2018-10-25
申请号：US15493352
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Joydeep Ray , Abhishek R. Appu , Subramaniam M. Maiyuran , Eric J. Hoekstra , Prasoonkumar Surti , Balaji Vembu , Altug Koker
CPC classification number: G06T1/20 , G06F9/4831 , G06F9/4881 , G06F9/505 , G06T2210/52
Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.
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公开(公告)号：US20180293692A1
公开(公告)日：2018-10-11
申请号：US15482808
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T1/20 , G06F9/3009 , G06F9/30185 , G06F9/3851 , G06F9/461 , G06F9/4843
Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
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公开(公告)号：US09846962B2
公开(公告)日：2017-12-19
申请号：US14865200
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Kalyan K. Bhiravabhatla , Subramaniam M. Maiyuran , Saurabh Sharma
CPC classification number: G06T15/30 , G06T11/40 , G06T15/005 , G06T15/80
Abstract: Marking “Clipped Triangles” as visible triangles for all tiles may be avoided by instead finding an approximate clipping area and marking the triangles as visible only in those tiles in the Position Only Shading Pipe (POSH) pipe. This avoids rendering the triangle in the replay pipe in those tiles where it may not be visible.
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公开(公告)号：US12131402B2
公开(公告)日：2024-10-29
申请号：US17749275
申请日：2022-05-20
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T1/20 , G06F9/3009 , G06F9/30185 , G06F9/3851 , G06F9/461 , G06F9/4843
Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.
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