公开(公告)号：US20190103346A1

公开(公告)日：2019-04-04

申请号：US15845531

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20180366457A1

公开(公告)日：2018-12-20

申请号：US15781798

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L21/4882 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (TC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

公开(公告)号：US20180286797A1

公开(公告)日：2018-10-04

申请号：US15473317

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Eng Huat Goh

IPC: H01L23/498 ,  H03H7/38 ,  H01L21/48 ,  H01L23/50 ,  H01L23/528 ,  H01L23/522 ,  H01L23/492 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4871 ,  H01L23/4924 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2223/6627 ,  H01L2223/6655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.

公开(公告)号：US10014710B2

公开(公告)日：2018-07-03

申请号：US14964466

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Mark A. Schaecher ,  Teong Guan Yew ,  Eng Huat Goh

IPC: H02J7/02 ,  H02J50/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H02J7/025 ,  H01F27/36 ,  H01F38/14 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/552 ,  H01L25/18 ,  H01L25/50 ,  H02J50/10

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

公开(公告)号：US20160216731A1

公开(公告)日：2016-07-28

申请号：US14604531

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Khai Ern See ,  Damien Weng Kong Chong ,  Min Suet Lim ,  Ping Ping Ooi ,  Chu Aun Lim ,  Jimmy Huat Since Huang ,  Poh Tat Oh ,  Teong Keat Beh ,  Jackson Chung Peng Kong ,  Fern Nee Tan ,  Jenn Chuan Cheng

IPC: G06F1/16 ,  H05K1/18 ,  G06F1/18 ,  G06F13/38

CPC classification number: G06F1/163 ,  G06F1/16 ,  G06F1/1656 ,  G06F1/187 ,  G06F13/38 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

Abstract translation: 实施例一般涉及利用计算机在包装结构上的装置。 计算机的一个实施例包括基板; 一个或多个半导体器件，所述一个或多个半导体器件是直接芯片附着到所述衬底，所述一个或多个半导体器件包括中央处理单元（CPU）; 以及安装在基板上的一个或多个附加部件，其中计算机不包括I / O部件。

公开(公告)号：US20250052512A1

公开(公告)日：2025-02-13

申请号：US18447951

申请日：2023-08-10

Applicant: Intel Corporation

Inventor： Shantanu Kulkarni ,  Jeff Ku ,  Baomin Liu ,  Tongyan Zhai ,  Min Suet Lim ,  Chee Chun Yee ,  Eng Huat Goh ,  Jun Liao ,  Kavitha Nagarajan

IPC: F28D15/04

Abstract: Systems, apparatus, articles of manufacture, and methods related to multi-sectional vapor chambers for electronic devices are disclosed. An example vapor chamber includes a first panel, a second panel, and a wall extending between the first panel and the second panel to separate the vapor chamber into a first section and a second section between both the first panel and the second panel, the wall including insulation.

公开(公告)号：US20250008685A1

公开(公告)日：2025-01-02

申请号：US18216049

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Nirmala Bailur ,  Min Suet Lim ,  Tongyan Zhai ,  Chee Chun Yee ,  Ruander Cardenas ,  Lance Lin ,  Eng Huat Goh ,  Javed Shaikh ,  Jun Liao ,  Kavitha Nagarajan ,  Tin Poay Chuah ,  Martin M. Chang ,  Shantanu D. Kulkarni ,  Telesphor Kamgaing

IPC: H05K7/20 ,  F04D19/00 ,  F04D29/52 ,  G06F1/20

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for cooling electronic devices. An example apparatus includes a fan module for an electronic device. The fan module includes a first cover; a second cover; an input/output (IO) board adjacent the second cover, the second cover and IO board beneath the first cover; and a fan between the first cover and the second cover, the fan to operate above the second cover and a portion of the IO board.

公开(公告)号：US11929295B2

公开(公告)日：2024-03-12

申请号：US17677843

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L23/3121 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/82 ,  H01L2924/01029 ,  H01L2924/1811

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US20240006399A1

公开(公告)日：2024-01-04

申请号：US17853329

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Chan Kim Lee ,  Eng Huat Goh ,  Jenny Shio Yin Ong ,  Tin Poay Chuah

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/552

CPC classification number: H01L25/18 ,  H01L25/0652 ,  H01L23/3185 ,  H01L23/367 ,  H01L25/50 ,  H01L21/56 ,  H01L21/486 ,  H01L23/552 ,  H01L23/5386

Abstract: An electronic device includes a package substrate; a memory integrated circuit (IC) mounted on the package substrate; a mold layer including one or more chiplets and a base IC die within the mold layer, the one or more chiplets arranged on the base IC die; a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC; and a heat spreader having a uniform surface contacting the memory IC and the top chiplet.

公开(公告)号：US20230091395A1

公开(公告)日：2023-03-23

申请号：US17483670

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Mooi Ling Chang ,  Poh Boon Khoo ,  Chu Aun Lim ,  Min Suet Lim ,  Prabhat Ranjan

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: Integrated circuit (IC) packages with On Package Memory (OPM) architectures are disclosed herein. An example IC package includes a substrate having a first side and a second side opposite the first side, a semiconductor die mounted on the first side of the substrate, and a die pad on the first side of the substrate. The die is electrically coupled to the die pad. The IC package also includes a memory pad on the first side of the substrate. The memory pad is to be electrically coupled to a memory mounted on the first side of the substrate. The IC package further includes a ball on the second side of the substrate, and a memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball.