Flexible substrate attaching method and flexible substrate attachment structure
    32.
    发明授权
    Flexible substrate attaching method and flexible substrate attachment structure 有权
    柔性基板贴附方法和柔性基板附着结构

    公开(公告)号:US09544995B2

    公开(公告)日:2017-01-10

    申请号:US14761986

    申请日:2015-02-10

    Inventor: Ce Ning Tao Gao

    Abstract: The present disclosure relates to the technical field of flexible substrate processing, and discloses a flexible substrate attaching method. The flexible substrate attaching method comprises the steps of: pre-fixing a flexible substrate on a carrier substrate with a first fixation structure; forming a thin film on the flexible substrate, and forming a pattern of the thin film via a patterning process; the pattern of the thin film contacting at least a part of the flexible substrate and at least a part of the carrier substrate simultaneously to play the function of consolidating the flexible substrate onto the carrier substrate. In this flexible substrate attaching method, a flexible substrate can be fixed on a carrier substrate and the flexible panel can be detached after the manufacture is completed. The present disclosure further provides a flexible substrate attachment structure.

    Abstract translation: 本公开涉及柔性基板加工的技术领域,并且公开了一种柔性基板附着方法。 柔性基板安装方法包括以下步骤:利用第一固定结构将柔性基板预固定在载体基板上; 在柔性基板上形成薄膜,并通过图案化工艺形成薄膜图案; 所述薄膜的图案与所述柔性基板的至少一部分和所述载体基板的至少一部分同时接触,以发挥将所述柔性基板固结到所述载体基板上的功能。 在这种柔性基板安装方法中,可以将柔性基板固定在载体基板上,并且在制造完成之后可以将柔性板分离。 本公开进一步提供了柔性基板附接结构。

    Thin film transistor array substrate and producing method thereof
    34.
    发明授权
    Thin film transistor array substrate and producing method thereof 有权
    薄膜晶体管阵列基板及其制造方法

    公开(公告)号:US09240424B2

    公开(公告)日:2016-01-19

    申请号:US14127245

    申请日:2012-11-21

    Inventor: Ce Ning Zhijun Lv

    CPC classification number: H01L27/127 H01L27/1225 H01L27/124 H01L27/1288

    Abstract: Disclosed are a thin film transistor array substrate and a producing method thereof in the embodiments of the present invention, the producing method comprising: forming an active layer thin film and a conductive layer thin film on a substrate; depositing a source/drain electrode layer thin film on the conductive layer thin film, treating the conductive layer thin film and the source/drain electrode layer thin film using gray tone or half tone masking process, to form at least two data lines, a pixel electrode and source/drain electrodes of the thin film transistor (TFT); after depositing an insulating layer thin film covered the active layer thin film, the source/drain electrodes, the data lines and the pixel electrode, forming a through hole and a gate insulating layer of the TFT on the insulating layer, to form an active layer of the TFT; forming a gate electrode of the TFT and at least two gate scanning lines cross with the data wires.

    Abstract translation: 公开了本发明实施例中的薄膜晶体管阵列基板及其制造方法,所述制造方法包括:在基板上形成有源层薄膜和导电层薄膜; 在导电层薄膜上沉积源极/漏极层薄膜,使用灰度色调或半色调掩蔽处理处理导电层薄膜和源极/漏极层薄膜,以形成至少两条数据线,像素 薄膜晶体管(TFT)的电极和源/漏电极; 在沉积覆盖有源层薄膜,源极/漏极,数据线和像素电极的绝缘层薄膜之后,在绝缘层上形成TFT的通孔和栅极绝缘层,以形成有源层 的TFT; 形成TFT的栅极电极和至少两个栅极扫描线与数据线交叉。

    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND PRODUCING METHOD THEREOF
    35.
    发明申请
    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND PRODUCING METHOD THEREOF 有权
    薄膜晶体管阵列基板及其制造方法

    公开(公告)号:US20140117372A1

    公开(公告)日:2014-05-01

    申请号:US14127245

    申请日:2012-11-21

    Inventor: Ce Ning Zhijun Lv

    CPC classification number: H01L27/127 H01L27/1225 H01L27/124 H01L27/1288

    Abstract: Disclosed are a thin film transistor array substrate and a producing method thereof in the embodiments of the present invention, the producing method comprising: forming an active layer thin film and a conductive layer thin film on a substrate; depositing a source/drain electrode layer thin film on the conductive layer thin film, treating the conductive layer thin film and the source/drain electrode layer thin film using gray tone or half tone masking process, to form at least two data lines, a pixel electrode and source/drain electrodes of the thin film transistor (TFT); after depositing an insulating layer thin film covered the active layer thin film, the source/drain electrodes, the data lines and the pixel electrode, forming a through hole and a gate insulating layer of the TFT on the insulating layer, to form an active layer of the TFT; forming a gate electrode of the TFT and at least two gate scanning lines cross with the data wires.

    Abstract translation: 公开了本发明实施例中的薄膜晶体管阵列基板及其制造方法,所述制造方法包括:在基板上形成有源层薄膜和导电层薄膜; 在导电层薄膜上沉积源极/漏极层薄膜,使用灰度色调或半色调掩蔽处理处理导电层薄膜和源极/漏极层薄膜,以形成至少两条数据线,像素 薄膜晶体管(TFT)的电极和源/漏电极; 在沉积覆盖有源层薄膜,源极/漏极,数据线和像素电极的绝缘层薄膜之后,在绝缘层上形成TFT的通孔和栅极绝缘层,以形成有源层 的TFT; 形成TFT的栅极电极和至少两个栅极扫描线与数据线交叉。

    Display substrate, display panel and display apparatus

    公开(公告)号:US12235554B2

    公开(公告)日:2025-02-25

    申请号:US18026489

    申请日:2022-06-22

    Abstract: A display substrate, a display panel and a display apparatus. The display substrate includes a first base substrate; a plurality of gate lines and a plurality of data lines which are arranged on a side of the first base substrate; the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other; a planarization layer, arranged on a side of the gate lines and the data lines away from the first base substrate, and including a first via hole; and a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole; and in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole.

    Shift register unit, gate driving circuit and display device

    公开(公告)号:US12230340B2

    公开(公告)日:2025-02-18

    申请号:US17996293

    申请日:2021-11-30

    Abstract: The present disclosure provides a shift register unit, a gate driving circuit and a display device. The shift register unit provided by the present disclosure includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, at least one pull-down sub-circuit, at least one first noise reduction sub-circuit, and a reverse bias sub-circuit; the reverse bias sub-circuit is configured to control transistors in at least part of sub-circuits connected to a pull-up node to be in a reverse bias state through a power voltage signal in response to a potential of the pull-up node, or control the transistors in at least part of the sub-circuits connected to the pull-up node to be in the reverse bias state through a cascade signal in response to a potential of a cascade signal terminal.

    Biochip and manufacturing method thereof

    公开(公告)号:US12226772B2

    公开(公告)日:2025-02-18

    申请号:US17432580

    申请日:2021-01-22

    Abstract: A biochip and a method for manufacturing the same are provided. The biochip includes: a guide layer; a channel layer on the guide layer, wherein the channel layer has therein a plurality of first channels extending in a first direction; a plurality of second channels extending in a second direction, wherein each of the plurality of second channels is in communication with the plurality of first channels, the plurality of second channels are in a layer where the channel layer is located, or in a layer where the channel layer and the guide layer are located; an encapsulation cover plate on a side of the channel layer distal to the guide layer; and a driving unit configured to drive biomolecules to move.

    Liquid crystal display panel and display apparatus

    公开(公告)号:US12222607B2

    公开(公告)日:2025-02-11

    申请号:US18024004

    申请日:2022-05-27

    Abstract: The disclosure provides a liquid crystal display panel and a display apparatus. The liquid crystal display panel of the disclosure includes: first and second substrates assembled to form a cell, a plurality of main spacers therebetween, and an auxiliary spacer around at least a portion of the main spacers. Height of the auxiliary spacer is greater than or equal to that of the main spacer. The display panel further includes: pillows on side of the first substrate close to the second substrate and each abutting against a corresponding main spacer. An orthographic projection of the main spacer on the first substrate falls within an orthographic projection of the pillow on the first substrate, and an orthographic projection of the auxiliary spacer on the first substrate does not overlap with the orthographic projection of the pillow on the first substrate.

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