公开(公告)号：US10191086B2

公开(公告)日：2019-01-29

申请号：US15079364

申请日：2016-03-24

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Zhao Wang ,  Ajay Bhatia

IPC: G11C7/00 ,  G01R15/09 ,  G01R31/40

Abstract: An apparatus for detecting a change in a voltage level of a power supply is disclosed. An inverter coupled to a first power supply may generate a signal dependent upon a voltage level of a second power supply. A latch coupled to the first power supply may be set based on a first voltage level of the second power supply and a first value of the signal, and re-set based on a second voltage level of the second power supply and a second value of the signal different than the first value of the signal.

公开(公告)号：US20180308772A1

公开(公告)日：2018-10-25

申请号：US16017801

申请日：2018-06-25

Applicant: Apple Inc.

Inventor： Michael R. Seningen

IPC: H01L21/66 ,  H01L29/66 ,  H01L21/67 ,  H01L21/321 ,  B23K26/351 ,  G01R31/28 ,  G01R31/26 ,  H01L21/268 ,  B23K26/00 ,  B23K101/42

CPC classification number: H01L22/20 ,  B23K26/351 ,  B23K26/352 ,  B23K26/354 ,  B23K26/361 ,  B23K26/50 ,  B23K31/125 ,  B23K2101/42 ,  G01R31/2621 ,  G01R31/2851 ,  H01L21/268 ,  H01L21/67115 ,  H01L21/67288 ,  H01L22/14 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66568

Abstract: Methods and apparatuses for modifying a work function of transistors included in an integrated circuit are disclosed. A tester unit may be configured to test an integrated circuit that includes a plurality of circuit paths. The tester unit may be further configured to analyze the results from testing the integrated circuit and, based on the analysis, identify a circuit path that fails to meet a desired performance goal. A work function of a transistor included in the identified circuit path may be modified by the tester unit using an energy source external to the integrated circuit.

公开(公告)号：US09013933B2

公开(公告)日：2015-04-21

申请号：US14294318

申请日：2014-06-03

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C7/22 ,  G11C11/418 ,  G11C29/12 ,  G11C29/50 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

Abstract translation: 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。 存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。 第一读出放大器的增益电平可以高于第二读出放大器的增益电平。 输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。 输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出可以被设置为高阻抗状态。

公开(公告)号：US20250165404A1

公开(公告)日：2025-05-22

申请号：US19029681

申请日：2025-01-17

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20240393394A1

公开(公告)日：2024-11-28

申请号：US18323946

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Bo Yang ,  Antonietta Oliva ,  Michael R. Seningen ,  Vasu P. Ganti ,  Vijay M. Bettada

IPC: G01R31/3185

Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

公开(公告)号：US20240134792A1

公开(公告)日：2024-04-25

申请号：US18360352

申请日：2023-07-26

Applicant: Apple Inc.

Inventor： Michael R. Seningen

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.

公开(公告)号：US20220269617A1

公开(公告)日：2022-08-25

申请号：US17662500

申请日：2022-05-09

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20220101914A1

公开(公告)日：2022-03-31

申请号：US17317844

申请日：2021-05-11

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Ajay Bhatia ,  Michael R. Seningen ,  Greg M. Hess ,  Siddhesh Gaiki

IPC: G11C11/412 ,  G11C11/419 ,  G06F7/523

Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

公开(公告)号：US20220100655A1

公开(公告)日：2022-03-31

申请号：US17033587

申请日：2020-09-25

Applicant: Apple Inc.

Inventor： Michael R. Seningen

IPC: G06F12/0802

Abstract: A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.

公开(公告)号：US20190089354A1

公开(公告)日：2019-03-21

申请号：US15710406

申请日：2017-09-20

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Michael R. Seningen ,  Ajay Bhatia

IPC: H03K19/00 ,  H03K5/134

Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.