公开(公告)号：US12072810B2

公开(公告)日：2024-08-27

申请号：US18475890

申请日：2023-09-27

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20220269617A1

公开(公告)日：2022-08-25

申请号：US17662500

申请日：2022-05-09

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US09495318B2

公开(公告)日：2016-11-15

申请号：US14089237

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Jim J. Lin ,  Timothy R. Paaske ,  Ben D. Jarrett

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/362 ,  G06F13/364

CPC classification number: G06F13/405 ,  G06F13/362 ,  G06F13/364 ,  G06F13/4027

Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。

公开(公告)号：US20130074020A1

公开(公告)日：2013-03-21

申请号：US13675362

申请日：2012-11-13

Applicant: Apple Inc.

Inventor： Ben D. Jarrett

IPC: G06F17/50

CPC classification number: G06F17/5059 ,  G06F17/504 ,  G06F2217/84

Abstract: A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic.

Abstract translation: 用于识别和去除冗余信号路径的方法包括确定对逻辑电路的给定输入是否耦合到时钟状态元件的数据输入的逻辑锥的输入端和耦合以禁用 时钟输入到时钟状态元素。 该方法可以包括从逻辑圆锥去除给定的输入，使得给定的输入不再耦合到逻辑锥的输入，响应于确定给定输入耦合到逻辑锥的输入和 时钟门电路。 该方法可以包括将给定的输入保持到时钟门电路，使得给定输入在从逻辑锥的输入移除之后继续耦合到时钟门电路。

公开(公告)号：US20150227410A1

公开(公告)日：2015-08-13

申请号：US14179191

申请日：2014-02-12

Applicant: Apple Inc.

Inventor： Ben D. Jarrett ,  Fritz A. Boehm

IPC: G06F11/07 ,  G01R31/3177

CPC classification number: G06F11/0778 ,  G01R31/31705 ,  G06F11/22 ,  G06F11/3476 ,  G06F17/40

Abstract: Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.

Abstract translation: 利用硬件状态数据记录器在硅中进行调试的系统和方法。 将一个或多个硬件状态数据记录器结合到电路设计中并与电路的功能单元一起制造成制造的芯片。 当在制造的芯片的测试期间遇到问题时，硬件状态数据记录器能够捕获并存储导致错误的最终事件序列。 然后从制造的芯片中提取存储的数据，并用于确定故障的根本原因。

公开(公告)号：US08543962B2

公开(公告)日：2013-09-24

申请号：US13675362

申请日：2012-11-13

Applicant: Apple Inc.

Inventor： Ben D. Jarrett

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5059 ,  G06F17/504 ,  G06F2217/84

Abstract: A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic.

Abstract translation: 用于识别和去除冗余信号路径的方法包括确定对逻辑电路的给定输入是否耦合到时钟状态元件的数据输入的逻辑锥的输入端和耦合以禁用 时钟输入到时钟状态元素。 该方法可以包括从逻辑圆锥去除给定的输入，使得给定的输入不再耦合到逻辑锥的输入，响应于确定给定输入耦合到逻辑锥的输入和 时钟门电路。 该方法可以包括将给定的输入保持到时钟门电路，使得给定输入在从逻辑锥的输入移除之后继续耦合到时钟门电路。

公开(公告)号：US20250103122A1

公开(公告)日：2025-03-27

申请号：US18807525

申请日：2024-08-16

Applicant: Apple Inc.

Inventor： Angel E. Socarras ,  Ben D. Jarrett ,  Jason P. Jane ,  Thomas B. Pringle ,  Andrea Gianarro ,  Jackson Dsouza

IPC: G06F1/3206 ,  G06F11/34 ,  G06F11/36

Abstract: Techniques are disclosed relating to power management in a processing circuit that includes a set of functional blocks and performance counter registers configured to store utilization values indicative of utilization of associated ones of the set of functional blocks. A register interface circuit is configured to periodically sample the processing circuit to obtain aggregated utilization values generated from utilization values stored in the performance counter registers and write the aggregated utilization values to the set of trace buffer. A power management processor is configured to utilize a set of information stored in the set of trace buffers to determine whether to change a performance state of the processing circuit, the set of information including time-domain and frequency-domain representations of utilization of the processing circuit. In other embodiments, a functional block that is a hardware limiter of the processing circuit may be determined.

公开(公告)号：US11803480B2

公开(公告)日：2023-10-31

申请号：US17662500

申请日：2022-05-09

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US10691610B2

公开(公告)日：2020-06-23

申请号：US16124166

申请日：2018-09-06

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20150149673A1

公开(公告)日：2015-05-28

申请号：US14089237

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Jim J. Lin ,  Timothy R. Paaske ,  Ben D. Jarrett

IPC: G06F13/40 ,  G06F13/362

CPC classification number: G06F13/405 ,  G06F13/362 ,  G06F13/364 ,  G06F13/4027

Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。