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    Control of A Computer System in A Power-Down State
    2.
    发明申请
    Control of A Computer System in A Power-Down State 有权

    公开(公告)号：US20230066750A1

    公开(公告)日：2023-03-02

    申请号：US18049239

    申请日：2022-10-24

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Josh P. de Cesare

    IPC: G06F1/3287 ,  G06F1/26 ,  G06F9/4401

    Abstract: Techniques are disclosed relating a computer system in a power-down state receiving a communication from a remote computer system and performing a task indicated by the communication. The computer system in a power-down state performs the task without transitioning from the power-down state into a power-up state. Exemplary tasks performed in the power-down state include uploading one or more files to a remote computer system, downloading one or more files from a remote computer system, deleting one or more files from the computer system, accessing input/output devices, disabling the computer system, and performing a memory check on the computer system.

    System power management using communication bus protocols
    5.
    发明授权
    System power management using communication bus protocols 有权

    公开(公告)号：US10551907B2

    公开(公告)日：2020-02-04

    申请号：US15184190

    申请日：2016-06-16

    Applicant: Apple Inc.

    Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

    IPC: G06F1/3296 ,  G06F1/06 ,  G06F1/3206 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/08 ,  G06F1/3237

    Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

    Synchronizing transactions for a single master over multiple busses
    7.
    发明授权
    Synchronizing transactions for a single master over multiple busses 有权
    通过多个总线同步单个主站的事务

    公开(公告)号：US09495318B2

    公开(公告)日：2016-11-15

    申请号：US14089237

    申请日：2013-11-25

    Applicant: Apple Inc.

    Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Jim J. Lin ,  Timothy R. Paaske ,  Ben D. Jarrett

    IPC: G06F13/00 ,  G06F13/40 ,  G06F13/362 ,  G06F13/364

    CPC classification number: G06F13/405 ,  G06F13/362 ,  G06F13/364 ,  G06F13/4027

    Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

    Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。

    Embedded encryption/secure memory management unit for peripheral interface controller
    9.
    发明授权
    Embedded encryption/secure memory management unit for peripheral interface controller 有权
    用于外设接口控制器的嵌入式加密/安全内存管理单元

    公开(公告)号：US09256551B2

    公开(公告)日：2016-02-09

    申请号：US13963457

    申请日：2013-08-09

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  David S. Warren ,  Michael J. Smith ,  Diarmuid P. Ross ,  Weihua Mao

    IPC: H04L29/06 ,  G06F12/14 ,  H04L9/12 ,  G06F21/60 ,  G06F21/72 ,  G06F21/85 ,  G06F21/87 ,  G09C1/00

    CPC classification number: G06F12/1408 ,  G06F21/602 ,  G06F21/72 ,  G06F21/85 ,  G06F21/87 ,  G09C1/00 ,  H04L9/12 ,  H04L2209/12

    Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

    Abstract translation: 在一个实施例中，外围接口控制器可以包括内联密码引擎，其可以对通过外围接口发送的数据进行加密，并解密从外围接口接收的数据。 加密可能对连接到正在接收/提供数据的外设接口的设备是透明的。 在一个实施例中，外围接口控制器包括在芯片上的系统（SOC）中，该系统还包括被配置为耦合到存储器的存储器控​​制器。 存储器可以以片上芯片或封装的封装形式安装在SOC上。 未加密的数据可以存储在存储器中以供SOC的其他部分使用（例如处理器，片上外设等）。 用于加密/解密数据的密钥可能保留在SOC内。

    Secure Public Key Acceleration
    10.
    发明申请
    Secure Public Key Acceleration 有权

    公开(公告)号：US20250053667A1

    公开(公告)日：2025-02-13

    申请号：US18774305

    申请日：2024-07-16

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Mitchell D. Adler ,  Conrad Sauerwald ,  Fabrice L. Gautier ,  Shu-Yi Yu

    IPC: G06F21/60 ,  G06F21/32 ,  G06F21/62 ,  G06F21/71 ,  G09C1/00 ,  H04L9/08 ,  H04L9/30 ,  H04L9/32

    Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.

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