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公开(公告)号：US20150089259A1
公开(公告)日：2015-03-26
申请号：US14032335
申请日：2013-09-20
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
CPC classification number: G06F1/3296 , G06F1/06 , G06F1/08 , G06F1/3206 , G06F1/3237 , G06F1/325 , G06F13/4022 , G06F13/4282 , Y02D10/128 , Y02D10/151 , Y02D50/20
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
Abstract translation: 公开了可以允许管理计算系统的功率的装置和方法的实施例。 该装置可以包括时钟发生电路，总线接口单元和控制电路。 时钟发生电路可以被配置为产生多个时钟信号。 每个时钟信号可以提供与耦合到通信总线的设备内的不同功能块的定时参考。 总线接口单元可以被配置为经由通信总线从设备接收消息。 消息可以包括延迟值和激活低功率模式的请求。 控制电路可以被配置为取决于等待时间值和多个阈值的多个时钟信号中的一个或多个。
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公开(公告)号：US11181971B2
公开(公告)日：2021-11-23
申请号：US16780817
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
IPC: G06F1/3296 , G06F1/06 , G06F1/3206 , G06F13/40 , G06F13/42 , G06F1/3234 , G06F1/08 , G06F1/3237
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
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公开(公告)号：US08786332B1
公开(公告)日：2014-07-22
申请号：US13744004
申请日：2013-01-17
Applicant: Apple Inc.
Inventor： Erik P. Machnicki , David S. Warren , Shane J. Keil , Sukalpa Biswas
Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.
Abstract translation: 时钟分频器可以向逻辑块部分提供较低速度的时钟，但是在复位期间，时钟分频器可能无法正常工作，导致逻辑块部分在大于设计该逻辑的频率的时钟频率下复位。 然而，可以采用扩展复位，其中时钟分频器首先在逻辑块部分之前正常复位，从而允许根据分频时钟（例如，而不是更高速度的时钟）来复位该逻辑。 还可以采用异步复位，其中一个或多个时钟分频器首先在被提供有（同步的）高速时钟信号之前从复位中出现，使得时钟分频器彼此同相。 这可以使IC之间的不同区域之间的通信可能不会彼此正确相位。
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公开(公告)号：US20140197870A1
公开(公告)日：2014-07-17
申请号：US13744004
申请日：2013-01-17
Applicant: APPLE INC.
Inventor： Erik P. Machnicki , David S. Warren , Shane J. Keil , Sukalpa Biswas
IPC: H03L5/00
Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.
Abstract translation: 时钟分频器可以向逻辑块部分提供较低速度的时钟，但是在复位期间，时钟分频器可能无法正常工作，导致逻辑块部分在大于设计该逻辑的频率的时钟频率下复位。 然而，可以采用扩展复位，其中时钟分频器首先在逻辑块部分之前正常复位，从而允许根据分频时钟（例如，而不是更高速度的时钟）来复位该逻辑。 还可以采用异步复位，其中一个或多个时钟分频器首先在被提供有（同步的）高速时钟信号之前从复位中出现，使得时钟分频器彼此同相。 这可以使IC之间的不同区域之间的通信可能不会彼此正确相位。
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5.发明申请Embedded Encryption/Secure Memory Management Unit for Peripheral Interface Controller 有权用于外围接口控制器的嵌入式加密/安全内存管理单元公开(公告)号：US20150046702A1
公开(公告)日：2015-02-12
申请号：US13963457
申请日：2013-08-09
Applicant: Apple Inc.
Inventor： Timothy R. Paaske , David S. Warren , Michael J. Smith , Diarmuid P. Ross , Weihua Mao
CPC classification number: G06F12/1408 , G06F21/602 , G06F21/72 , G06F21/85 , G06F21/87 , G09C1/00 , H04L9/12 , H04L2209/12
Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.
Abstract translation: 在一个实施例中，外围接口控制器可以包括内联密码引擎，其可以对通过外围接口发送的数据进行加密，并解密从外围接口接收的数据。 加密可能对连接到正在接收/提供数据的外设接口的设备是透明的。 在一个实施例中，外围接口控制器包括在芯片上的系统（SOC）中，该系统还包括被配置为耦合到存储器的存储器控制器。 存储器可以以片上芯片或封装的封装形式安装在SOC上。 未加密的数据可以存储在存储器中以供SOC的其他部分使用（例如处理器，片上外设等）。 用于加密/解密数据的密钥可能保留在SOC内。
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Patent Agency Ranking
公开(公告)号：US10551907B2
公开(公告)日：2020-02-04
申请号：US15184190
申请日：2016-06-16
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
IPC: G06F1/3296 , G06F1/06 , G06F1/3206 , G06F13/40 , G06F13/42 , G06F1/3234 , G06F1/08 , G06F1/3237
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
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公开(公告)号：US20160291685A1
公开(公告)日：2016-10-06
申请号：US15184190
申请日：2016-06-16
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
CPC classification number: G06F1/3296 , G06F1/06 , G06F1/08 , G06F1/3206 , G06F1/3237 , G06F1/325 , G06F13/4022 , G06F13/4282 , Y02D10/128 , Y02D10/151 , Y02D50/20
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
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8.发明授权Embedded encryption/secure memory management unit for peripheral interface controller 有权用于外设接口控制器的嵌入式加密/安全内存管理单元公开(公告)号：US09256551B2
公开(公告)日：2016-02-09
申请号：US13963457
申请日：2013-08-09
Applicant: Apple Inc.
Inventor： Timothy R. Paaske , David S. Warren , Michael J. Smith , Diarmuid P. Ross , Weihua Mao
CPC classification number: G06F12/1408 , G06F21/602 , G06F21/72 , G06F21/85 , G06F21/87 , G09C1/00 , H04L9/12 , H04L2209/12
Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.
Abstract translation: 在一个实施例中，外围接口控制器可以包括内联密码引擎，其可以对通过外围接口发送的数据进行加密，并解密从外围接口接收的数据。 加密可能对连接到正在接收/提供数据的外设接口的设备是透明的。 在一个实施例中，外围接口控制器包括在芯片上的系统（SOC）中，该系统还包括被配置为耦合到存储器的存储器控制器。 存储器可以以片上芯片或封装的封装形式安装在SOC上。 未加密的数据可以存储在存储器中以供SOC的其他部分使用（例如处理器，片上外设等）。 用于加密/解密数据的密钥可能保留在SOC内。
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公开(公告)号：US20200174550A1
公开(公告)日：2020-06-04
申请号：US16780817
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
IPC: G06F1/3296 , G06F13/42 , G06F13/40 , G06F1/3206 , G06F1/06 , G06F1/3237 , G06F1/08 , G06F1/3234
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
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公开(公告)号：US09395795B2
公开(公告)日：2016-07-19
申请号：US14032335
申请日：2013-09-20
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
CPC classification number: G06F1/3296 , G06F1/06 , G06F1/08 , G06F1/3206 , G06F1/3237 , G06F1/325 , G06F13/4022 , G06F13/4282 , Y02D10/128 , Y02D10/151 , Y02D50/20
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
Abstract translation: 公开了可以允许管理计算系统的功率的装置和方法的实施例。 该装置可以包括时钟发生电路，总线接口单元和控制电路。 时钟发生电路可以被配置为产生多个时钟信号。 每个时钟信号可以提供与耦合到通信总线的设备内的不同功能块的定时参考。 总线接口单元可以被配置为经由通信总线从设备接收消息。 消息可以包括延迟值和激活低功率模式的请求。 控制电路可以被配置为取决于等待时间值和多个阈值的多个时钟信号中的一个或多个。
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